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90 nm process

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Template:Short description Template:Use dmy dates Template:About Template:Refimprove Template:Semiconductor manufacturing processes The 90 nm process refers to the technology used in semiconductor manufacturing to create integrated circuits with a minimum feature size of 90 nanometers. It was an advancement over the previous 130 nm process. Eventually, it was succeeded by smaller process nodes, such as the 65 nm, 45 nm, and 32 nm processes.

It was commercialized by the 2003–2005 timeframe, by semiconductor companies including Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology.

The origin of the 90 nm value is historical; it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).

The 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.

The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;<ref name="urlNo More Nanometers – EEJournal">{{#invoke:citation/CS1|citation |CitationClass=web }}</ref> neither gate length, metal pitch or gate pitch on a "90nm" device is ninety nanometers.<ref>{{#invoke:citation/CS1|citation |CitationClass=web }}</ref><ref>{{#invoke:citation/CS1|citation |CitationClass=web }}</ref><ref>{{#invoke:citation/CS1|citation |CitationClass=web }}</ref><ref>{{#invoke:citation/CS1|citation |CitationClass=web }}</ref>

HistoryEdit

A 90Template:Nbspnm silicon MOSFET was fabricated by Iranian engineer Ghavam Shahidi (later IBM director) with D.A. Antoniadis and H.I. Smith at MIT in 1988. The device was fabricated using X-ray lithography.<ref>Template:Cite journal</ref>

Toshiba, Sony and Samsung developed a 90Template:Nbspnm process during 2001Template:Ndash2002, before being introduced in 2002 for Toshiba's eDRAM and Samsung's 2Template:NbspGb NAND flash memory.<ref>Template:Cite news</ref><ref name="samsung2000s">{{#invoke:citation/CS1|citation |CitationClass=web }}</ref> IBM demonstrated a 90Template:Nbspnm silicon-on-insulator (SOI) CMOS process, with development led by Shahidi, in 2002. The same year, Intel demonstrated a 90Template:Nbspnm strained-silicon process.<ref>Template:Cite news</ref> Fujitsu commercially introduced its 90Template:Nbspnm process in 2003<ref name="fujitsu">{{#invoke:citation/CS1|citation |CitationClass=web }}</ref> followed by TSMC in 2004.<ref>{{#invoke:citation/CS1|citation |CitationClass=web }}</ref>

Gurtej Singh Sandhu of Micron Technology initiated the development of atomic layer deposition high-k films for DRAM memory devices. This helped drive cost-effective implementation of semiconductor memory, starting with 90Template:Nbspnm node DRAM.<ref name="ieee">{{#invoke:citation/CS1|citation |CitationClass=web }}</ref>

Intel's 90nm process has a transistor density of 1.45 million transistors per square millimeter (MTr/mm2).<ref>{{#invoke:citation/CS1|citation |CitationClass=web }}</ref>

Example: Elpida 90 nm DDR2 SDRAM processEdit

Elpida Memory's 90 nm DDR2 SDRAM process.<ref>Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report</ref>

  • Use of 300 mm wafer size
  • Use of KrF (248 nm) lithography with optical proximity correction
  • 512 Mbit
  • 1.8 V operation
  • Derivative of earlier 110 nm and 100 nm processes

Processors using 90 nm process technologyEdit

See alsoEdit

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ReferencesEdit

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External linksEdit

Preceded by
{{#if:130 nm|130 nm|—}} 		MOSFET manufacturing processes{{#if:|
{{{curr}}}}} 		Succeeded by
{{#if:65 nm|65 nm|—}}
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