Editing 90 nm process (section)

{{short description|Semiconductor device fabrication technology node}}
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{{About|semiconductor manufacturing|the spaceport with FAA LID code of 90NM|Spaceport America}}
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{{Semiconductor manufacturing processes}}
The '''90 nm process''' refers to the technology used in [[semiconductor manufacturing]] to create [[integrated circuit]]s with a minimum feature size of 90 nanometers. It was an advancement over the previous [[130 nm process]]. Eventually, it was succeeded by smaller process nodes, such as the [[65 nm]], [[45 nm]], and [[32 nm process]]es.

It was commercialized by the 2003–2005 timeframe, by semiconductor companies including [[Toshiba]], [[Sony]], [[Samsung]], [[IBM]], [[Intel]], [[Fujitsu]], [[TSMC]], [[Elpida Memory|Elpida]], [[AMD]], [[Infineon]], [[Texas Instruments]] and [[Micron Technology]].

The origin of the 90&nbsp;nm value is historical; it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the [[International Technology Roadmap for Semiconductors]] (ITRS).

The 300&nbsp;mm wafer size became mainstream at the 90&nbsp;nm node. The previous wafer size was 200&nbsp;mm diameter.

The 193&nbsp;[[nanometre|nm]] wavelength was introduced by many (but not all) companies for [[photolithography|lithography]] of critical layers mainly during the 90&nbsp;nm node. Yield issues associated with this transition (due to the use of new [[photoresist]]s) were reflected in the high costs associated with this transition.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;<ref name="urlNo More Nanometers – EEJournal">{{cite web |url=https://www.eejournal.com/article/no-more-nanometers/ |title=No More Nanometers – EEJournal |date=23 July 2020 |format= }}</ref> neither gate length, metal pitch or gate pitch on a "90nm" device is ninety nanometers.<ref>{{cite web|url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|title=A Brief History of Process Node Evolution|last=Shukla|first=Priyank|website=design-reuse.com|access-date=2019-07-09}}</ref><ref>{{cite web|url=https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|title=14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists...|last=Hruska|first=Joel|website=[[ExtremeTech]]|date=23 June 2014 }}</ref><ref>{{cite web|url=https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|title=Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022|website=wccftech.com|date=2016-09-10}}</ref><ref>{{cite web|url=https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|title=Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms|website=eejournal.com|date=2018-03-12}}</ref>