Editing ARM architecture family (section)

{{Short description|Family of computer architectures}}
{{Redirect|ARM architecture|the Australian architectural firm|ARM Architecture (company)}}
{{Use British English|date=June 2012}}<!--Possibly we want to make exceptions for technical non-British spelled words ARM uses like "virtualization"-->
{{Use dmy dates|date=July 2020}}
{{Infobox CPU architecture <!-- Common info belongs in this infobox -->
|name         = ARM
|image        = Arm logo 2025.svg
|designer     = {{plainlist|
* [[Sophie Wilson]]
* [[Steve Furber]]
* [[Acorn Computers]]/[[Arm Holdings]]}}
|bits         = [[32-bit computing|32-bit]], [[64-bit computing|64-bit]]
|introduced   = {{Start date and age|1985|df=yes}}
|design       = [[Reduced instruction set computer|RISC]]
|type         = [[Load–store architecture|Load–store]]
|branching    = [[Status register|Condition code]], compare and branch
|open         = Proprietary
}}
{{Infobox CPU architecture<!-- 64-bit architecture info belongs in this infobox -->
|image        = AArch64 logo.svg
|name         = ARM ''AArch64'' (64/32-bit)
|introduced   = {{start date and age|2011|df=yes}}
|version      = ARMv8-R, ARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A, ARMv8.5-A, ARMv8.6-A, ARMv8.7-A, ARMv8.8-A, ARMv8.9-A, ARMv9.0-A, ARMv9.1-A, ARMv9.2-A, ARMv9.3-A, ARMv9.4-A, ARMv9.5-A, ARMv9.6-A <!--note ARMv8-M does not really fit here or anywhere as only 32-bit.-->
|encoding     = [[AArch64]]/A64 and [[#AArch32|AArch32]]/A32 use 32-bit instructions, AArch32/T32 (Thumb-2) uses mixed 16- and 32-bit instructions<ref name="v8arch"/>
|endianness   = [[Endianness#Bi-endianness|Bi]] (little as default)
|extensions   = <!--Complementary: --> [[ARMv8-A SVE|SVE]], SVE2, SME, AES, SM3, SM4, SHA, CRC32, RNDR, TME; All mandatory: [[#Thumb-2|Thumb-2]], [[#Advanced SIMD (Neon)|Neon]], VFPv4-D16, VFPv4; obsolete: [[#Thumb|Thumb]] and [[Jazelle]]
|gpr          = 31 × 64-bit integer registers<ref name="v8arch"/>
|fpr          = 32 × [[128-bit computing|128-bit]] registers<ref name="v8arch"/> for scalar 32- and 64-bit [[IEEE 754|FP]] or [[single instruction, multiple data|SIMD]] FP or integer; or cryptography
}}
{{Infobox CPU architecture <!-- 32-bit Cortex architecture info belongs in this infobox -->
|name         = ARM ''AArch32'' (32-bit)
|introduced   = <!-- please investigate the years each of these architectures were announced -->
|version      = ARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M
|encoding     = 32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions.
|endianness   = [[Bi-endian|Bi]] (little as default)
|extensions   = [[#Thumb|Thumb]], [[#Thumb-2|Thumb-2]], [[#Advanced SIMD (Neon)|Neon]], [[Jazelle]], AES, SM3, SM4, SHA, CRC32, RNDR, DSP, Saturated, FPv4-SP, FPv5, Helium; obsolete since ARMv8: [[#Thumb|Thumb]] and [[Jazelle]]
|gpr          = 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC)
|fpr          = Up to 32 × 64-bit registers,<ref>{{cite web |url=https://github.com/ARM-software/abi-aa/blob/2a70c42d62e9c3eb5887fa50b71257f20daca6f9/aapcs32/aapcs32.rst#6121vfp-register-usage-conventions |title=6.1.2.1 VFP register usage conventions |work=Procedure Call Standard for the ARM Architecture |publisher=[[Arm Holdings]] |date=6 October 2023 |access-date=22 August 2024}}</ref> SIMD/floating-point (optional)
}}
{{Infobox CPU architecture <!-- 32-bit legacy architecture info belongs in this infobox -->
|name         = ARM 32-bit (legacy)
|introduced   = <!-- please investigate the years each of these architectures were announced -->
|version      = ARMv6, ARMv5, ARMv4T, ARMv3, ARMv2
|encoding     = 32-bit, except Thumb extension uses mixed 16- and 32-bit instructions.
|endianness   = [[Bi-endian|Bi]] (little as default) in ARMv3 and above
|extensions   = [[ARM Thumb|Thumb]], [[Jazelle]] <!-- please investigate and clarify -->
|gpr          = 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older)
|fpr          = None
}}

'''ARM''' (stylised in lowercase as '''arm''', formerly an acronym for '''Advanced RISC Machines''' and originally '''Acorn RISC Machine''') is a family of [[reduced instruction set computer|RISC]] [[instruction set architecture]]s (ISAs) for [[central processing unit|computer processors]]. [[Arm Holdings]] develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses [[semiconductor intellectual property core|cores]] that implement these ISAs.

Due to their low costs, low power consumption, and low heat generation, ARM processors are useful for light, portable, battery-powered devices, including [[smartphone]]s, [[laptop]]s, and [[tablet computer]]s, as well as [[embedded system]]s.<ref name="ARM1">{{cite newsgroup |url=https://groups.google.com/group/comp.arch/msg/269fe7defd51f29e |title=Some facts about the Acorn RISC Machine |author-link=Sophie Wilson |first=Roger |last=Wilson |newsgroup=comp.arch |date=2 November 1988 |access-date=25 May 2007}}</ref><ref name="extremetech-3g-territory">{{cite news |url=https://www.extremetech.com/extreme/52180-arm-cores-climb-into-3g-territory |title=ARM Cores Climb into 3G Territory |date=14 October 2002 |first=Mark |last=Hachman |work=ExtremeTech |access-date=24 May 2018}}</ref><ref>{{cite news |url=https://www.embedded.com/the-two-percent-solution/ |title=The Two Percent Solution |last=Turley |first=Jim |work=Embedded |date=18 December 2002 |access-date=14 February 2023}}</ref> However, ARM processors are also used for [[desktop computer|desktops]] and [[server (computing)|server]]s, including [[Fugaku (supercomputer)|Fugaku]], the world's fastest [[supercomputer]] from 2020<ref>{{cite news |last1=Cutress |first1=Ian |title=New #1 Supercomputer: Fujitsu's Fugaku and A64FX take Arm to the Top with 415 PetaFLOPs |url=https://www.anandtech.com/show/15869/new-1-supercomputer-fujitsus-fugaku-and-a64fx-take-arm-to-the-top-with-415-petaflops |access-date=2021-01-25 |work=anandtech.com |date=22 June 2020}}</ref> to 2022. With over 230 billion ARM chips <!--thereof at least 130 billion ARM processors--> produced,<ref>{{cite press release |title=Arm Partners Have Shipped 200 Billion Chips |url=https://www.arm.com/blogs/blueprint/200bn-arm-chips |access-date=2021-11-03 |website=Arm |language=en}}</ref><ref>{{cite web |url=https://community.arm.com/iot/b/internet-of-things/posts/enabling-mass-iot-connectivity-as-arm-partners-ship-100-billion-chips |title=Enabling Mass IoT connectivity as ARM partners ship 100 billion chips |website=community.arm.com |date=27 February 2017 |quote=the cumulative deployment of 100 billion chips, half of which shipped in the last four years. [..] why not a trillion or more? That is our target, seeing a trillion connected devices deployed over the next two decades. |access-date=8 April 2020}}</ref> {{as of|2024|alt=since at least 2003, and with its dominance increasing every year}},<!-- source for older 2014 claim:<ref>{{cite news |last=Robinson |first=Tracy |date=12 February 2014 |url=https://community.arm.com/community/news/blog/2014/02/12/celebrating-50-billion-shipped-arm-powered-chips |title=Celebrating 50 Billion shipped ARM-powered Chips |access-date=31 January 2016}}</ref> --> ARM is the most widely used family of instruction set architectures.<ref>{{cite web |url=https://www.icinsights.com/news/bulletins/MCU-Market-On-Migration-Path-To-32bit-And-ARMbased-Devices/ |title=MCU Market on Migration Path to 32-bit and ARM-based Devices: 32-bit tops in sales; 16-bit leads in unit shipments |publisher=IC Insights |date=25 April 2013 |access-date=1 July 2014}}</ref><ref name="extremetech-3g-territory"/><ref>{{cite web |last=Turley |first=Jim |year=2002 |title=The Two Percent Solution |url=https://www.embedded.com/electronics-blogs/significant-bits/4024488/The-Two-Percent-Solution |archive-url=https://web.archive.org/web/20230215003436/https://www.embedded.com/the-two-percent-solution/ |archive-date=15 February 2023 |publisher=embedded.com}}</ref><ref>{{cite web |url=https://www.theregister.co.uk/2011/02/01/arm_holdings_q4_2010_numbers/ |title=Arm Holdings eager for PC and server expansion |website=[[The Register]] |date=1 February 2011|author-first1=Timothy|author-last1=Prickett Morgan}}</ref><ref>{{cite news |last=McGuire-Balanza |first=Kerry |date=11 May 2010 |url=https://community.arm.com/groups/internet-of-things/blog/2010/05/11/arm-from-zero-to-billions-in-25-short-years |title=ARM from zero to billions in 25 short years |publisher=[[Arm Holdings]] |access-date=8 November 2012|url-access=registration}}</ref>

There have been several generations of the ARM design. The original ARM1 used a [[32-bit computing|32-bit]] internal structure but had a 26-bit [[address space]] that limited it to 64&nbsp;MB of [[main memory]]. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A architecture added support for a [[64-bit computing|64-bit]] address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.<ref name="armv8-a-announcement">{{cite press release |url=https://www.arm.com/about/newsroom/arm-discloses-technical-details-of-the-next-version-of-the-arm-architecture.php |title=ARM Discloses Technical Details of the Next Version of the ARM Architecture |date=27 October 2011 |publisher=[[Arm Holdings]] |access-date=20 September 2013 |archive-url=https://web.archive.org/web/20190101024118/https://www.arm.com/about/newsroom/arm-discloses-technical-details-of-the-next-version-of-the-arm-architecture.php |archive-date=1 January 2019}}</ref> Arm Holdings has also released a series of additional instruction sets for different roles: the "Thumb" extensions add both 32- and 16-bit instructions for improved [[code density]], while [[Jazelle]] added instructions for directly handling [[Java bytecode]]. More recent changes include the addition of [[simultaneous multithreading]] (SMT) for improved performance or [[fault tolerance]].<ref>{{cite web |url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure |title=Announcing the ARM Neoverse N1 Platform |website=community.arm.com |date=20 February 2019 |access-date=8 April 2020}}</ref>