Editing AltiVec (section)

{{short description|SIMD instruction set extension for the PowerPC ISA}}
{{POWER, PowerPC, and Power ISA}}
'''AltiVec''' is a single-precision [[floating point]] and integer [[SIMD]] [[instruction set]] designed and owned by [[Apple Inc.|Apple]], [[IBM]], and [[Freescale Semiconductor]] (formerly [[Motorola]]'s Semiconductor Products Sector) &mdash; the [[AIM alliance]].  It is implemented on versions of the [[PowerPC]] processor architecture, including Motorola's [[PowerPC G4|G4]], [[IBM]]'s [[PowerPC 970|G5]] and [[POWER6]] processors, and [[P.A. Semi]]'s [[PWRficient]] PA6T.  AltiVec is a [[trademark]] owned solely by Freescale, so the system is also referred to as '''Velocity Engine''' by Apple and '''VMX''' ('''Vector Multimedia Extension''') by IBM and P.A. Semi.

While AltiVec refers to an instruction set, the implementations in CPUs produced by IBM and Motorola are separate in terms of logic design. To date, no IBM core has included an AltiVec logic design licensed from Motorola or vice versa.

AltiVec is a standard part of the [[Power ISA#Power ISA v.2.03|Power ISA v.2.03]]<ref name="isa203">{{cite web
 |title     = Power ISA v.2.03
 |publisher     = Power.org
 |url     = http://www.power.org/resources/downloads/PowerISA_203_Final_Public.pdf
 |access-date     = 2024-08-09
 |archive-date     = 2011-07-27
 |archive-url     = https://web.archive.org/web/20110727183430/http://www.power.org/resources/downloads/PowerISA_203_Final_Public.pdf
 |url-status     = bot: unknown
 }}</ref> specification. It was never formally a part of the PowerPC architecture until this specification although it used [[PowerPC]] instruction formats and syntax and occupied the [[opcode]] space expressly allocated for such 
purposes.