Editing Back-side bus (section)

{{Short description|Computer architecture terminology}}
In [[personal computer]] [[microprocessor]] architecture, a '''back-side bus''' ('''BSB'''), or '''backside bus''', was a [[Bus (computing)|computer bus]] used on early Intel platforms to connect the [[Central processing unit|CPU]] to [[CPU cache|CPU cache memory]], usually off-die L2. If a design utilizes a back-side bus along with a [[front-side bus]] (FSB), the design is said to use a '''dual-bus architecture''', or in [[Intel Corporation|Intel]]'s terminology ''[[Dual independent bus|Dual Independent Bus]]'' (DIB)<ref>{{cite web|url=http://www.pcguide.com/ref/cpu/arch/extBackside-c.html|title=Dedicated Backside Cache Bus|publisher=PCguide.com|date=2001-04-30}}</ref> architecture. The back-side bus architecture evolved when newer processors like [[Coppermine (microprocessor)|the second-generation Pentium III]] began to incorporate on-die L2 cache, which at the time was advertised as ''Advanced Transfer Cache'', but Intel continued to refer to the Dual Independent Bus till the end of Pentium III.<ref>[http://download.intel.com/design/intarch/prodbref/27331106.pdf Pentium® III Processors for Applied Computing product brief]</ref>

[[File:Intel MMC2 arch.svg|450px]]