Editing CAS latency (section)

{{short description|Time delay between data read command and availability of data in a computer's RAM}}
{{original research|date=July 2019}}

'''Column address strobe latency''', also called '''CAS latency''' or '''CL''', is the delay in clock cycles between the READ command and the moment data is available.<ref>{{cite web|url=http://archive.arstechnica.com/paedia/r/ram_guide/ram_guide.part2-5.html|archive-url=https://web.archive.org/web/20121101003215if_/http://archive.arstechnica.com:80/paedia/r/ram_guide/ram_guide.part2-5.html|title=Ars Technica RAM Guide Part II: Asynchronous and Synchronous DRAM|last=Stokes|first=Jon "Hannibal"|publisher=Ars Technica|date=1998–2004|archive-date=2012-11-01 }}</ref><ref name=umd>{{citation|title=Synchronous DRAM Architectures, Organizations, and Alternative Technologies|publisher=University of Maryland|last=Jacob|first=Bruce L.|date=December 10, 2002|url=https://user.eng.umd.edu/~blj/CS-590.26/references/DRAM-Systems.pdf}}</ref> In asynchronous [[Dynamic random-access memory|DRAM]], the interval is specified in nanoseconds (absolute time).<ref name=async>{{citation |title=Memory technology evolution: an overview of system memory technologies|publisher=HP|date=July 2008|url=https://support.hpe.com/hpsc/doc/public/display?docId=emr_na-c01552458}}</ref>  In [[synchronous dynamic random-access memory|synchronous DRAM]], the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of absolute time, the actual time for an [[SDRAM]] module to respond to a CAS event might vary between uses of the same module if the clock rate differs.