Editing COP8 (section)

{{about|COP8 microcontroller|8th Climate Change Conference of the Parties|2002 United Nations Climate Change Conference}}
{{Short description|8-bit microcontroller}}
{{Infobox CPU
|name           = National Semiconductor COP8
|produced-start = {{Start date and age|1988}}
|numinstructions = 69
|produced-end   = 
|data-width     = 8 (RAM), 8 (ROM)
|address-width  = 8 (RAM), 15 (ROM)
|slowest        = 0 | slow-unit = Hz
|fastest        = 2 | fast-unit = MHz
|transistors    = 
|manuf1         = [[National Semiconductor]]
|application    = Embedded
|arch           = COP8
|pack1          = 20, 28, and 40-pin [[Dual in-line package|DIP]]; 16, 20, and 28 pin [[Small outline integrated circuit|SOIC]]; 44-pin [[Chip carrier|PLCC]]
|predecessor    = [[COP400]]
|successor      = none
}}

The [[National Semiconductor]] '''COP8''' is an 8-bit [[Complex instruction set computer|CISC]] core [[microcontroller]]. COP8 is an enhancement to the earlier [[COP400]] 4-bit microcontroller family. COP8 main features are:

* Large amount of [[I/O]] pins
* Up to 32&nbsp;KB of [[Flash memory]]/[[Read-only memory|ROM]] for code and data 
* Very low [[Electromagnetic interference|EMI]]
* Many integrated peripherals (meant as single chip design)
* [[In-System Programming]]
* Free [[Assembly language|assembler]] toolchain. Commercial [[C (programming language)|C]] compilers available
* Free Multitasking OS and [[TCP/IP]] stack
* Peak of 2 million instructions per second

The COP8 has a basic instruction cycle time 1/10 of the clock frequency; a maximum 10&nbsp;MHz clock will result in a maximum 1&nbsp;MHz instruction execution rate.  (The 10&nbsp;MHz clock is used directly by some timer peripherals.)   The maximum instruction execution rate is 1 cycle per byte, and most 1-byte instructions operate in one instruction cycle.  Some, particularly branch instructions, take one or two cycles more.  Some models include a clock doubler, and although they still accept a maximum 10&nbsp;MHz input clock, they internally double it to a 20&nbsp;MHz master clock which then results in a 2&nbsp;MHz instruction execution rate.{{r|cop8s|p=7,32}}

The chip is a [[static logic]] design which can tolerate an arbitrarily slow clock;{{r|cop8s|p=10}} most models include a second {{val|32768|u=Hz}} [[quartz clock]] crystal oscillator which can be used for the CPU clock while the high-speed clock is disabled to save power.