Editing Classic RISC pipeline (section)

{{Short description|Instruction pipeline}}
{{Use American English|date = March 2019}}
{{More footnotes|date=December 2012}}

In the [[history of computing hardware|history of computer hardware]], some early [[reduced instruction set computer]] [[central processing unit]]s (RISC CPUs) used a very similar architectural solution, now called a '''classic RISC pipeline'''. Those CPUs were: [[MIPS architecture|MIPS]], [[SPARC]], Motorola [[Motorola 88000|88000]], and later the notional CPU [[DLX]] invented for education.

Each of these classic scalar RISC designs fetches and tries to execute one [[Instructions per cycle|instruction per cycle]].  The main common concept of each design is a five-stage execution [[instruction pipeline]].  During operation, each pipeline stage works on one instruction at a time.  Each of these stages consists of a set of [[flip-flop (electronics)|flip-flops]] to hold state, and [[combinational logic]] that operates on the outputs of those flip-flops.