Editing DDR2 SDRAM (section)

{{short description|Second generation of double-data-rate synchronous dynamic random-access memory}}
{{Infobox memory
| abbr       = DDR2 SDRAM
| name       = Double Data Rate 2 Synchronous Dynamic Random-Access Memory
| image      = Swissbit 2GB PC2-5300U-555.jpg
| caption    = Front and back of a 2GB PC2-5300 DDR2 RAM module for desktop PCs (DIMM)
| developer  = [[Samsung]]<ref name="phys"/> <br /> [[JEDEC]]
| type       = [[Synchronous dynamic random-access memory]]
| generation = 2nd generation
| release    = {{Start date and age|2003|09}}
| standards  = {{Unbulleted list|DDR2-400 (PC2-3200)|DDR2-533 (PC2-4200)|DDR2-667 (PC2-5300)|DDR2-800 (PC2-6400)|DDR2-1066 (PC2-8500)}}
| clock_rate = {{Nowrap|100–266 MHz}}
| cycle_time = {{Nowrap|10–3.75 ns}}
| prefetch   = 4n
| bus_clock_rate = {{Nowrap|200–533 MHz}}
| transfer_rate  = {{Nowrap|400–1066 MT/s}}
| bandwidth = {{Nowrap|3,200–8,533 MB/s}}
| voltage   = {{Nowrap|1.8 V}}
| predecessor = [[DDR SDRAM]]
| successor = [[DDR3 SDRAM]]
}}
'''Double Data Rate 2 Synchronous Dynamic Random-Access Memory''' ('''DDR2 SDRAM''') is a [[double data rate]] (DDR) [[synchronous dynamic random-access memory]] (SDRAM) [[External memory interface|interface]]. It is a [[JEDEC]] standard (JESD79-2); first published in September 2003.<ref>{{Cite web |date=2003-09-12 |title=JEDEC Publishes DDR2 Standard |url=http://www.jedec.org/Home/press/press_release/jedec_publishes_DD2Std.pdf |url-status=dead |archive-url=https://web.archive.org/web/20031204212300/http://www.jedec.org/home/press/press_release/jedec_publishes_DD2Std.pdf |archive-date=2003-12-04}}</ref> DDR2 succeeded the original [[DDR SDRAM]] specification, and was itself succeeded by [[DDR3 SDRAM]] in 2007. DDR2 [[DIMM]]s are neither [[Forward compatibility|forward compatible]] with DDR3 nor [[Backward compatibility|backward compatible]] with DDR.

In addition to double pumping the data [[Bus (computing)|bus]] as in DDR SDRAM (transferring data on the rising and falling edges of the bus [[clock signal]]), DDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. The two factors combine to produce a total of four data transfers per internal clock cycle.

Since the DDR2 internal clock runs at half the DDR external clock rate, DDR2 memory operating at the same external data bus clock rate as DDR results in DDR2 being able to provide the same [[Bandwidth (computing)|bandwidth]] but with better [[Memory timings|latency]]. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules.
The maximum capacity on commercially available DDR2 DIMMs is 8GB, but chipset support and availability for those DIMMs is sparse and more common 2GB per DIMM are used.{{Citation needed|date=June 2019}}<ref>https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/modules/parity_rdimm/htf36c256_512_1gx72pz.pdf?rev=e8e3928f09794d61809f92abf36bfb24 {{Bare URL PDF|date=March 2022}}</ref>