Editing Dataflow architecture (section)

{{Short description|Type of low-level computer architecture}}
{{More citations needed|date=August 2012}}
'''Dataflow architecture''' is a [[dataflow]]-based [[computer architecture]] that directly contrasts the traditional [[von Neumann architecture]] or [[control flow]] architecture. Dataflow architectures have no [[program counter]], in concept: the executability and execution of instructions is solely determined based on the availability of input arguments to the instructions,<ref name=architecture>{{cite journal |last=Veen |first=Arthur H. |date=December 1986 |title=Dataflow Machine Architecture |journal=ACM Computing Surveys |volume=18 |number=4 |pages=365–396 |url=https://www.researchgate.net/publication/220566271 |access-date=5 March 2019 |doi=10.1145/27633.28055 |s2cid=5467025}}</ref> so that the order of instruction execution may be hard to predict.  

Although no commercially successful general-purpose computer hardware has used a dataflow architecture, it has been successfully implemented in specialized hardware such as in [[digital signal processing]], [[network routing]], [[graphics processing]], [[telemetry]], and more recently in data warehousing, and [[artificial intelligence]] (as: polymorphic dataflow<ref>{{Cite news |last=Maxfield |first=Max |date=24 December 2020 |title=Say Hello to Deep Vision's Polymorphic Dataflow Architecture |work=Electronic Engineering Journal |publisher=Techfocus media}}</ref> Convolution Engine,<ref>{{cite web |url=https://kinara.ai/<!-- Prior: https://deepvision.io/ --> |title=Kinara (formerly Deep Vision) |author=<!-- Unstated --> |date=2022 |website=Kinara |access-date=2022-12-11}}</ref> structure-driven,<ref>{{cite web |url=https://hailo.ai/ |title=Hailo |author=<!-- Unstated --> |date=<!-- Undated --> |website=Hailo |access-date=2022-12-11}}</ref> dataflow [[Scheduling (computing)|scheduling]]<ref>S. Lie, "Cerebras Architecture Deep Dive: First Look Inside the HW/SW Co-Design for Deep Learning : Cerebras Systems," ''2022 IEEE Hot Chips 34 Symposium (HCS)'', Cupertino, CA, USA, 2022, pp. 1-34, doi: 10.1109/HCS55958.2022.9895479. https://ieeexplore.ieee.org/document/9895479</ref>). It is also very relevant in many software architectures today including [[database]] engine designs and [[parallel computing]] frameworks.{{Citation needed|date=March 2015}}

Synchronous dataflow architectures tune to match the workload presented by real-time data path applications such as wire speed packet forwarding. Dataflow architectures that are deterministic in nature enable programmers to manage complex tasks such as processor [[Load balancing (computing)|load balancing]], synchronization and accesses to common resources.<ref name="EN-Genius">{{cite press release |date=June 18, 2008 |title=HX300 Family of NPUs and Programmable Ethernet Switches to the Fiber Access Market |url=http://www.en-genius.net/site/zones/networkZONE/product_reviews/netp_061608 |website=EN-Genius |url-status=dead |archive-url=https://web.archive.org/web/20110722151409/http://www.en-genius.net/site/zones/networkZONE/product_reviews/netp_061608 |archive-date=2011-07-22}}</ref> 

Meanwhile, there is a clash of terminology, since the term ''[[dataflow]]'' is used for a subarea of parallel programming: for [[dataflow programming]].