Editing Double data rate (section)

{{Short description|Method of computer bus operation}}
{{Use American English|date=September 2024}}

[[File:SDR DDR QDR.svg|thumb|A comparison between [[single data rate]], double data rate, and [[quad data rate]]. The dots are where data transfers take place, measured in millions of transfers per second (MT/s).]]

In [[computing]], '''double data rate''' ('''DDR''') describes a [[computer bus]] that transfers data on both the rising and falling edges of the [[clock signal]] and hence doubles the [[memory bandwidth]] by transferring data twice per clock cycle.<ref>{{cite book | url = https://books.google.com/books?id=pqYl3SWkA64C&pg=PA314 | isbn = 978-0-12-370490-0 | first1 = John L. | last1 = Hennessy | first2 = David A. | last2 = Patterson | year = 2007 | publisher = Morgan Kaufmann | location = Amsterdam | title = Computer architecture: a quantitative approach | page = 314}}</ref><ref name="Intel z434">{{cite web | title=double data rate (DDR) Definition | website=Intel | url=https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/reference/glossary/def_ddr.htm | access-date=2024-04-07}}</ref>  This is also known as '''double pumped''', '''dual-pumped''', and '''double transition'''.  The term '''toggle mode'''<!--boldface per WP:R#PLA--> is used in the context of [[NAND flash memory]].