Editing Emitter-coupled logic (section)

{{Short description|Integrated circuit logic family}}
{{Use mdy dates|date=September 2023}}
{{Use American English|date=September 2023}}
[[Image:ECL.svg|350px|thumb|right|Motorola ECL 10,000 basic [[OR gate|OR/NOR gate]] circuit diagram from 1972.<ref>Original drawing based on {{cite book |first=William R. |last=Blood Jr. |date=1972 |title=MECL System Design Handbook |edition=2nd  |publisher=Motorola Semiconductor Products |page=1 |url=http://www.bitsavers.org/components/motorola/_dataBooks/1972_Motorola_MECL_System_Design_Handbook_2ed.pdf |via=Bitsavers}}</ref>{{r|p=5|TND309}} Note the Q5 and Q6 emitters coupled to the output and the [[Emitter-coupled logic#power supply|negative-power supply]].{{efn|Motorolla ECL devices run off of a negative power supply. This "reversed" arrangement used to avoid noise that might be induced to the collector and emitter lines. It also had very unusual logic levels (see [[#logic_levels_comparison|comparison]]): -1.75 V for LOW (0) and -0.9 V for HIGH (1).{{r|p=5|TND309}} It was possible to design circuits by using ECL with positive sources (see PECL - Positive ECL).{{r|p=18|TND309}} }}<ref>{{Cite book |url=https://www.onsemi.com/download/application-notes/pdf/an1406-d.pdf |title=Designing with PECL (ECL at +5.0V), The High Speed Solution for the CMOS/TTL Designer |date=September 1999 |publisher=Onsemi |edition=2 }}</ref> ]]

In electronics, '''emitter-coupled logic''' ('''ECL''') is a high-speed [[integrated circuit]] bipolar transistor [[logic family]]. ECL uses a [[bipolar junction transistor]] (BJT) [[differential amplifier]] with single-ended input and limited emitter current to avoid the [[Bipolar junction transistor#Regions of operation|saturated]] (fully on) region of operation and the resulting slow turn-off behavior.<ref name = "unitd04">
{{cite web
 | url = http://www.physics.dcu.ie/~bl/digi/unitd04.pdf
 | work = Fundamental Digital Electronics
 | first = Brian |last=Lawless
 | title = Unit4: ECL Emitter Coupled Logic
 }}</ref>
As the current is steered between two legs of an emitter-coupled pair, ECL is sometimes called ''current-steering logic'' (CSL),<ref>
{{cite book
 | title = Pulse and Digital Circuits
 | first = Anand |last=Kumar
 | publisher = PHI Learning
 | year = 2008
 | isbn = 978-81-203-3356-7
 | page = 472
 | url = https://books.google.com/books?id=ECeObhzCiLIC&pg=RA2-PA472
}}</ref>
''current-mode logic'' (CML)<ref>
{{cite book
 | title = Digital Logic Techniques: Principles and Practice
 | first = T. J. |last=Stonham
 | publisher = Taylor & Francis
 | year = 1996
 | isbn = 978-0-412-54970-0
 | page = 173
 | url = https://books.google.com/books?id=UE6vFEnGP2kC&pg=PA173
}}</ref>
or ''current-switch emitter-follower'' (CSEF) logic.<ref>
{{cite book
 | title = Fundamentals of Microsystems Packaging
 | first = Rao R. |last=Tummala
 | publisher = McGraw-Hill
 | year = 2001
 | pages = 930
 | url = https://books.google.com/books?id=P93ZrOWHlO0C&pg=PA930
 | isbn = 978-0-07-137169-8
 }}</ref>

In ECL, the transistors are never in saturation, the input and output voltages have a small swing (0.8 V), the input impedance is high and the output impedance is low. As a result, the transistors change states quickly, [[gate delay]]s are low, and the [[fanout]] capability is high.<ref>
{{cite book
 | title = The Forrest Mims Circuit Scrapbook
 | volume = 2
 | first = Forrest M. |last=Mims
 | author-link = Forrest Mims
 | publisher = Newnes
 | year = 2000
 | isbn = 978-1-878707-48-2
 | page = 115
 | url = https://books.google.com/books?id=STzitya5iwgC&pg=PA115
 }}</ref> In addition, the essentially constant current draw of the differential amplifiers minimizes delays and [[Glitch#Electronics_glitch|glitches]] due to supply-line inductance and capacitance, and the complementary outputs decrease the propagation time of the whole circuit by reducing inverter count.

ECL's major disadvantage is that each gate continuously draws current, which means that it requires (and dissipates) significantly more power than those of other logic families, especially when quiescent.

The equivalent of emitter-coupled logic made from [[field-effect transistor|FETs]] is called [[source-coupled logic]] (SCFL).<ref>
{{cite book
 | title = Gallium Arsenide IC Applications Handbook
 | first1 = Dennis |last1=Fisher |first2=I.J. |last2=Bahl
 | publisher = Elsevier
 | year = 1995
 | isbn = 978-0-12-257735-2
 | page = 61
 | url = https://books.google.com/books?id=KSKJ56kvcSYC&pg=PA61
 | volume = 1
 }}</ref>

A variation of ECL in which all signal paths and gate inputs are differential is known as differential current switch (DCS) logic.<ref>
{{cite journal
 | first1 = E.B. |last1=Eichelberger |first2=S.E. |last2=Bello
 | date = May 1991
 | title = Differential Current Switch – High performance at low power
 | journal = IBM Journal of Research and Development
 | volume = 35
 | issue = 3
 | pages = 313–320
 | url = http://domino.watson.ibm.com/tchjr/journalindex.nsf/0/af4fa2f7f17243c485256bfa0067fab9?OpenDocument
 | doi = 10.1147/rd.353.0313
 | url-access = subscription
 }}</ref>