Editing Explicitly parallel instruction computing (section)

{{short description|Instruction set architecture}}
{{Refimprove|date=October 2010}}

'''Explicitly parallel instruction computing''' ('''EPIC''') is a term coined in 1997 by the [[Itanium|HP–Intel alliance]]<ref>{{cite web
|url = http://www.hpl.hp.com/techreports/1999/HPL-1999-111.pdf
|format=PDF|title = EPIC: An Architecture for Instruction-Level Parallel Processors
|access-date = 2008-05-08
|last = Schlansker and Rau
|work = HP Laboratories Palo Alto, HPL-1999-111
|date=February 2000
}}</ref> to describe a [[computing paradigm]] that researchers had been investigating since the early 1980s.<ref>{{cite patent|country=US|number=4847755|pubdate=1989-07-11|title=Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies|assign1=MCC Development Ltd.|inventor1-last=Morrison|inventor1-first=Gordon E.|inventor2-last=Brooks|inventor2-first=Christopher B.|inventor3-last=Gluck|inventor3-first=Frederick G.}}</ref> This paradigm is also called ''Independence'' architectures. It was the basis for [[Intel]] and [[Hewlett-Packard|HP]] development of the Intel [[Itanium]] architecture,<ref name="HP_Labs">{{cite web
| url = http://www.hpl.hp.com/news/2001/apr-jun/itanium.html
| title = Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture
| access-date = 2007-12-14
| date = June 2001
| work = [[Hewlett-Packard|HP]] Labs
| archive-date = 2012-03-04
| archive-url = https://web.archive.org/web/20120304045612/http://www.hpl.hp.com/news/2001/apr-jun/itanium.html
| url-status = dead
}}</ref> and [[Hewlett-Packard|HP]] later asserted that "EPIC" was merely an old term for the Itanium architecture.<ref name="anand">{{cite web
| url = http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2598
| title = Itanium&ndash;Is there light at the end of the tunnel?
| access-date = 2008-05-08
| last = De Gelas
| first = Johan
| date = November 9, 2005
| work = [[AnandTech]]
}}</ref> EPIC permits microprocessors to execute software instructions in parallel by using the [[compiler]], rather than complex on-[[die (integrated circuit)|die]] circuitry, to control parallel instruction execution. This was intended to allow simple performance scaling without resorting to higher [[clock rate|clock frequencies]].