Editing Hazard (computer architecture) (section)

{{Short description|Problems with the instruction pipeline in central processing unit (CPU) microarchitectures}}
{{More citations needed|date=January 2014}}
In the domain of [[central processing unit]] (CPU) [[CPU design|design]], '''hazards''' are problems with the [[instruction pipeline]] in CPU [[microarchitecture]]s when the next instruction cannot execute in the following clock cycle,{{sfn|Patterson|Hennessy|2009|p=335}} and can potentially lead to incorrect computation results. Three common types of hazards are data hazards, structural hazards, and control hazards (branching hazards).{{sfn|Patterson|Hennessy|2009|pp=335-343}}

There are several methods used to deal with hazards, including [[pipeline stall]]s/pipeline bubbling, [[#Operand forwarding|operand forwarding]], and in the case of [[out-of-order execution]], the [[scoreboarding]] method and the [[Tomasulo algorithm]].