Editing HyperTransport (section)

{{short description|Computer processor interconnection technology first introduced in 2001}}
{{distinguish |text=[[Hyper-Threading]], which is also sometimes abbreviated "HT"}}
{{Use mdy dates|date=November 2022}}
[[File:HyperTransport Consortium logo.svg|thumb|Logo of the HyperTransport Consortium]]

'''HyperTransport''' ('''HT'''), formerly known as '''Lightning Data Transport''', is a technology for interconnection of computer [[Processor (computing)|processor]]s.  It is a bidirectional [[Serial communication|serial]]/[[Parallel communication|parallel]] high-[[Bandwidth (computing)|bandwidth]], low-[[Memory latency|latency]] [[point-to-point link]] that was introduced on April 2, 2001.<ref>{{cite press release |title=API NetWorks Accelerates Use of HyperTransport Technology With Launch of Industry's First HyperTransport Technology-to-PCI Bridge Chip |url=http://www.hypertransport.org/consortium/cons_pressrelease.cfm?RecordID=62 |website=HyperTransport Consortium |date=April 2, 2001 |url-status=dead |archive-url=https://web.archive.org/web/20061010070210/http://www.hypertransport.org/consortium/cons_pressrelease.cfm?RecordID=62 |archive-date=October 10, 2006}}</ref>  The [[HyperTransport Consortium]] is in charge of promoting and developing HyperTransport technology.

HyperTransport is best known as the [[system bus]] architecture of [[AMD]] [[central processing unit]]s (CPUs) from [[Athlon 64]] through [[AMD FX]] and the associated [[motherboard]] chipsets. HyperTransport has also been used by [[IBM]] and [[Apple Inc.|Apple]] for the [[Power Mac G5]] machines, as well as a number of modern [[MIPS architecture|MIPS]] systems.

The current specification HTX 3.1 remained competitive for 2014 high-speed (2666 and 3200&nbsp;[[megatransfer|MT]]/s or about 10.4&nbsp;GB/s and 12.8&nbsp;GB/s) [[DDR4]] RAM and slower (around 1&nbsp;GB/s [http://www.extremetech.com/computing/175283-sandisk-announces-ulltra-dimms-terabytes-of-low-latency-flash-storage-directly-off-the-ram-channel] similar to high end [[Solid-state drive#Standard card form factors|PCIe SSDs]] [[ULLtraDIMM]] flash RAM) technology{{clarify|date=June 2015}}—a wider range of RAM speeds on a common CPU bus than any Intel [[front-side bus]].  Intel technologies require each speed range of RAM to have its own interface, resulting in a more complex motherboard layout but with fewer bottlenecks.  HTX 3.1 at 26&nbsp;GB/s can serve as a unified bus for as many as four DDR4 sticks running at the fastest proposed speeds. Beyond that DDR4 RAM may require two or more HTX 3.1 buses diminishing its value as unified transport.