Editing Instruction cycle (section)

{{Short description|Basic instruction cycle in a computer}}The '''instruction cycle''' (also known as the '''fetch–decode–execute cycle''', or simply the '''fetch–execute cycle''') is the cycle that the [[central processing unit]] (CPU) follows from [[booting|boot-up]] until the computer has shut down in order to process instructions. It is composed of three main stages: the fetch stage, the decode stage, and the execute stage. 
[[File:Fetch-Decode-Execute Cycle.png|thumb|This is a simple diagram illustrating the individual stages of the fetch-decode-execute cycle. Legend:
{{bulleted list
|PC – [[Program counter]]
|MAR – [[Memory address register]]
|MDR – [[Memory buffer register|Memory data register]]
|CIR – [[Instruction register|Current instruction register]]
|CU – [[Control unit]]
|ALU – [[Arithmetic logic unit]]
}}
]]
In simpler CPUs, the instruction cycle is executed sequentially, each instruction being processed before the next one is started. In most modern CPUs, the instruction cycles are instead executed [[concurrent computing|concurrently]], and often in [[parallel computing|parallel]], through an [[instruction pipeline]]: the next instruction starts being processed before the previous instruction has finished, which is possible because the cycle is broken up into separate steps.<ref>{{cite web |title=Pipelining |url=https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html |author=Crystal Chen, Greg Novick and Kirk Shimano |year=2000 |access-date=2019-06-26}}</ref>