Editing Instruction pipelining (section)

{{Short description|Method of improving instruction-level parallelism}}
{{Use American English|date = March 2019}}
{{More citations needed|date=May 2016}}
{| class="wikitable floatright" style="text-align:center; width:400px;"
|+[[Classic RISC pipeline|Basic five-stage pipeline]]
!{{diagonal split header|Instr. No.|Clock cycle}}
! style="width:2em" | 1
! style="width:2em" | 2
! style="width:2em" | 3
! style="width:2em; background: Lime" | 4
! style="width:2em" | 5
! style="width:2em" | 6
! style="width:2em" | 7
|-
|1
|IF
|ID
|EX
| style="background: red; color: white" | MEM
|WB
|
|
|-
|2
|
|IF
|ID
| style="background: Lime" | EX
|MEM
|WB
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|-
|3
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|
|IF
| style="background: Lime" | ID
|EX
|MEM
|WB
|-
|4
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| style="background: Lime" | IF
|ID
|EX
|MEM
|-
|5
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| style="background: Lime" | 
|IF
|ID
|EX
|-
| colspan="8" style="text-align:left" |(IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). 
In the fourth clock cycle (the green column), the earliest instruction is in MEM stage, and the latest instruction has not yet entered the pipeline.
|}

In [[computer engineering]], '''instruction pipelining''' is a technique for implementing [[instruction-level parallelism]] within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming [[Machine code|instructions]] into a series of sequential steps (the eponymous "[[Pipeline (computing)|pipeline]]") performed by different [[Central processing unit#Structure and implementation|processor units]] with different parts of instructions processed in parallel.