Editing Integrated circuit layout (section)

{{short description|Representation of an integrated circuit's components as planar shapes}}
[[File:Vlsiopamp2.gif|thumb|upright=1.8|Layout view of a simple CMOS operational amplifier]]

In [[integrated circuit design]], '''integrated circuit''' ('''IC''') '''layout''', also known '''IC mask layout''' or '''mask design''', is the representation of an [[integrated circuit]] in terms of planar [[geometric shape]]s which correspond to the patterns of [[metal]], [[silicon oxide|oxide]], or [[semiconductor]] layers that make up the components of the integrated circuit.  Originally the overall process was called [[tapeout]], as historically early ICs used graphical black [[Crêpe paper|crepe tape]] on [[mylar]] media for photo imaging (erroneously believed{{who|date=September 2020}} to reference magnetic data—the photo process greatly predated magnetic media{{citation needed|date=September 2020}}).  

When using a standard process—where the interaction of the many chemical, thermal, and photographic variables is known and carefully controlled—the behaviour of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes. Using a [[Computer-aided design|computer-aided layout tool]], the layout engineer—or layout technician—places and connects all of the components that make up the chip such that they meet certain criteria—typically: performance, size, density, and manufacturability. This practice is often subdivided between two primary layout disciplines: [[Analogue electronics|analog]] and [[Digital electronics|digital]].

The generated layout must pass a series of checks in a process known as physical verification. The most common checks in this verification process are<ref>A. Kahng, J. Lienig, I. Markov, J. Hu: ''VLSI Physical Design: From Graph Partitioning to Timing Closure'', {{doi|10.1007/978-3-030-96415-3}}, {{ISBN|978-3-030-96414-6}}, p. 9.</ref><ref>{{Cite journal|last=Basu|first=Joydeep|date=2019-10-09|title=From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology|journal=IETE Journal of Education|volume=60|issue=2|pages=51–64|doi=10.1080/09747338.2019.1657787|arxiv=1908.10674|s2cid=201657819}}</ref>

* [[Design rule checking]] (DRC), 
* [[Layout versus schematic]] (LVS),
* [[parasitic extraction]], 
* [[Physical verification#Antenna check|antenna rule checking]], and 
* [[Physical verification#Electrical rule check (ERC)|electrical rule checking]] (ERC).

When all verification is complete, [[mask data preparation|layout post processing]]<ref name="Layout_book">{{Cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|page=102-110|chapter=Chap. 3.3: Mask Data: Layout Post Processing|publisher=Springer|date=2020|doi=10.1007/978-3-030-39284-0|isbn=978-3-030-39284-0|s2cid=215840278}}</ref> is applied where the data is also translated into an industry-standard format, typically [[GDSII]], and sent to a [[Semiconductor fabrication plant|semiconductor foundry]]. The milestone completion of the layout process of sending this data to the foundry is now colloquially called "tapeout". The foundry converts the data into mask data<ref name="Layout_book" /> and uses it to generate the [[photomask]]s used in a [[photolithography|photolithographic]] process of [[Fabrication (semiconductor)|semiconductor device fabrication]].

In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, an evolution derived from early days of [[printed circuit board]] (PCB) design -- tape-out.

Modern IC layout is done with the aid of [[IC layout editor]] software, mostly automatically using [[electronic design automation|EDA tool]]s, including [[place and route]] tools or [[schematic-driven layout]] tools.
Typically this involves a library of [[standard cell]]s.

The manual operation of choosing and positioning the geometric shapes is informally known as "[[polygon]] pushing".<ref>
Dirk Jansen, editor.
[https://books.google.com/books?id=br3gBwAAQBAJ "The Electronic Design Automation Handbook"].
2010.
p. 39.
</ref><ref>
Dan Clein.
[https://books.google.com/books?id=fzuX6tyIeBkC "CMOS IC Layout: Concepts, Methodologies, and Tools"].
1999
p. 60.
</ref><ref>
[https://books.google.com/books?id=u4RVAAAAYAAJ "Conference Record"].
1987.
p. 118.
</ref><ref>
Charles A. Harper; Harold C. Jones.
[https://books.google.com/books?id=0bsQAQAAMAAJ "Active Electronic Component Handbook"].
1996.
p. 2
</ref><ref>
Riko Radojcic.
[https://books.google.com/books?id=R-5lDwAAQBAJ "Managing More-than-Moore Integration Technology Development"].
2018.
p. 99
</ref>