Editing Logic synthesis (section)

{{Short description|Process by which desired circuit behavior is turned into a schematic of logic gates}}
{{Distinguish|Synthetic programming}}
{{more citations needed|date=January 2013}}
{{use dmy dates|date=March 2021|cs1-dates=y}}
In [[computer engineering]], '''logic synthesis''' is a process by which an abstract specification of desired [[circuit (electronics)|circuit]] behavior, typically at [[register transfer level]] (RTL), is turned into a design implementation in terms of [[logic gates]], typically by a [[computer program]] called a ''synthesis tool''. Common examples of this process include synthesis of designs specified in [[Hardware Description Language|hardware description language]]s, including [[VHDL]] and [[Verilog]].<ref name="Verilog_2005"/> Some synthesis tools generate [[bitstream]]s for [[programmable logic device]]s such as [[programmable array logic|PAL]]s or [[Field-programmable gate array|FPGA]]s, while others target the creation of [[ASIC]]s. Logic synthesis is one step in circuit design in the [[electronic design automation]], the others are [[place and route]] and [[verification and validation]].