Editing MESI protocol (section)

{{Short description|Cache coherence protocol for computer processors}}
{{More citations needed|date=May 2023}}
The '''MESI protocol''' is an invalidate-based [[List of cache coherency protocols|cache coherence protocol]], and is one of the most common protocols that support [[write-back cache]]s. It is also known as the '''Illinois protocol''' due to its development at the [[University of Illinois Urbana-Champaign|University of Illinois at Urbana-Champaign]].<ref>{{Cite book | last1 = Papamarcos | first1 = M. S. | last2 = Patel | first2 = J. H. | doi = 10.1145/800015.808204 | chapter-url = http://www.csl.cornell.edu/courses/ece5720/papamarcos.isca84.pdf| access-date=March 19, 2013| chapter = A low-overhead coherence solution for multiprocessors with private cache memories | title = Proceedings of the 11th annual international symposium on Computer architecture - ISCA '84 | pages = 348 | year = 1984 | isbn = 0818605383 | s2cid = 195848872 }}</ref> Write back caches can save considerable bandwidth generally wasted on a [[Cache (computing)#Writing policies|write through cache]]. There is always a dirty state present in write-back caches that indicates that the data in the cache is different from that in the main memory. The Illinois Protocol requires a cache-to-cache transfer on a miss if the block resides in another cache. This protocol reduces the number of main memory transactions with respect to the [[MSI protocol]]. This marks a significant improvement in performance.<ref>{{Cite journal|last1 = Gómez-Luna | first1 = J. | last2 = Herruzo | first2 = E. | last3 = Benavides | first3 = J.I. |title=MESI Cache Coherence Simulator for Teaching Purposes|journal=Clei Electronic Journal|volume= 12| issue = 1, PAPER 5, APRIL 2009| citeseerx = 10.1.1.590.6891 }}</ref>