Editing MIPS architecture (section)

{{Short description|Instruction set architecture}}
{{Use mdy dates|date=November 2021}}
{{Infobox CPU architecture
| name       = MIPS
| designer   = [[MIPS Technologies]], [[Imagination Technologies]]
| bits       = [[64-bit]] (32 → 64)
| introduced = {{Start date and age|1985}}
| version    = MIPS32/64 Release 6 (2014)
| design     = [[Reduced instruction set computer|RISC]]
| type       = [[Load–store]]
| encoding   = Fixed
| branching  = Compare and branch, with a 1 instruction delay after the branching condition check
| endianness = [[Bi-endian|Bi]]
| page size  = 4&nbsp;KB
| extensions = [[MDMX]], [[MIPS-3D]]
| open       = Partly. The [[R10000#R16000|R16000]] processor has been on the market for more than 20 years and as such cannot be subject to patent claims. Therefore, the R16000 and older processors are fully open.
| gpr        = 32
| fpr        = 32
}}

'''MIPS''' ('''Microprocessor without Interlocked Pipelined Stages''')<ref>{{Cite book|title=Computer Organization and Design|last=Patterson|first=David|publisher=Elsevier|year=2014|isbn=978-0-12-407726-3|url=http://booksite.elsevier.com/9780124077263/downloads/historial%20perspectives/section_4.16.pdf|pages=4.16–4|access-date=November 28, 2018|archive-date=September 4, 2019|archive-url=https://web.archive.org/web/20190904223729/https://booksite.elsevier.com/9780124077263/downloads/historial%20perspectives/section_4.16.pdf|url-status=live}}</ref> is a family of [[reduced instruction set computer]] (RISC) [[instruction set architecture]]s (ISA)<ref name=Price1995>Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, Inc.</ref>{{rp|A-1}}<ref name=Sweetman1999>{{cite book|last=Sweetman|first=Dominic|date=1999|title=See MIPS Run|publisher=Morgan Kaufmann Publishers, Inc.|isbn=1-55860-410-3}}</ref>{{rp|19}} developed by MIPS Computer Systems, now [[MIPS Technologies]], based in the [[United States]].

There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6.<ref>{{cite web|url= https://www.mips.com/products/architectures/mips32-3/|title= MIPS32 Architecture|website= MIPS|access-date= March 20, 2020|archive-date= March 21, 2020|archive-url= https://web.archive.org/web/20200321031349/https://www.mips.com/products/architectures/mips32-3/|url-status= dead}}</ref><ref>{{cite web|url= https://www.mips.com/products/architectures/mips64/|title= MIPS64 Architecture|website= MIPS|access-date= March 20, 2020|archive-date= February 2, 2020|archive-url= https://web.archive.org/web/20200202235833/https://www.mips.com/products/architectures/mips64/|url-status= live}}</ref> MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.

The MIPS architecture has several optional extensions: [[MIPS-3D]], a simple set of [[floating-point]] [[Instruction set architecture#SIMD instruction|SIMD instructions]] dedicated to [[3D computer graphics]];<ref>{{cite web|url=http://www.imgtec.com/mips/mips-3d-ase.asp|title=MIPS-3D ASE|publisher=[[Imagination Technologies]]|archive-url=https://web.archive.org/web/20140103091950/http://www.imgtec.com/mips/mips-3d-ase.asp|archive-date=January 3, 2014|url-status=dead|access-date=January 4, 2014}}</ref> [[MDMX]] (MaDMaX), a more extensive integer [[Single instruction, multiple data|SIMD]] instruction set using 64-bit floating-point registers; MIPS16e, which adds [[compressed instructions|compression to the instruction stream]] to reduce the memory programs require;<ref>{{cite web|url=https://www.mips.com/products/architectures/ase/ase16e/|title=MIPS16e|website=MIPS|access-date=March 20, 2020|archive-date=January 16, 2021|archive-url=https://web.archive.org/web/20210116053233/https://www.mips.com/products/architectures/ase/ase16e/|url-status=live}}</ref> and MIPS MT, which adds [[Multithreading (computer architecture)|multithreading]] capability.<ref>{{cite web|url=https://www.mips.com/products/architectures/ase/multi-threading/|title=MIPS Multithreading|website=MIPS|access-date=March 20, 2020|archive-date=October 26, 2020|archive-url=https://web.archive.org/web/20201026011525/https://www.mips.com/products/architectures/ase/multi-threading/|url-status=live}}</ref>

[[Computer architecture]] courses in universities and technical schools often study the MIPS architecture.<ref>{{cite web|url=http://www.cs.ucdavis.edu/~peisert/teaching/ecs142-sp09/rt.html|title=ECS 142 (Compilers) References & Tools page|author=University of California, Davis|access-date=May 28, 2009|url-status=live|archive-url=https://web.archive.org/web/20110321052440/http://www.cs.ucdavis.edu/~peisert/teaching/ecs142-sp09/rt.html|archive-date=March 21, 2011}}</ref> The architecture greatly influenced later RISC architectures such as [[DEC Alpha|Alpha]]. In March 2021, MIPS announced that the development of the MIPS architecture had ended as the company is making the transition to [[RISC-V]].<ref name="mips-becomes-risc-v">{{cite web|url=https://www.eejournal.com/article/wait-what-mips-becomes-risc-v/|title=Wait, What? MIPS Becomes RISC-V|first=Jim|last=Turley|website=Electronic Engineering Journal|date=March 8, 2021|access-date=March 28, 2021|archive-date=March 21, 2021|archive-url=https://web.archive.org/web/20210321193838/https://www.eejournal.com/article/wait-what-mips-becomes-risc-v/|url-status=live}}</ref>