Editing Media-independent interface (section)

{{Short description|Type of computer networking connection}}
{{anchor|MII|SMII}}
{{Use American English|date = March 2019}}

[[File:Media independent interface (mii) connector on sun ultra 1.jpg|thumb|MII connector on a [[Sun Ultra series|Sun Ultra&nbsp;1]] Creator workstation]]

The '''media-independent interface''' ('''MII''') was originally defined as a standard interface to connect a [[Fast Ethernet]] (i.e., {{nowrap|100 Mbit/s}}) [[medium access control]] (MAC) block to a [[PHY#Ethernet physical transceiver|PHY chip]]. The MII is standardized by [[IEEE 802.3u]] and connects different types of PHYs to MACs. Being ''media independent'' means that different types of PHY devices for connecting to different media (i.e. [[Ethernet over twisted pair|twisted pair]], [[fiber optic]], etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission medium.

The MII can be used to connect a MAC to an external PHY using a pluggable connector or directly to a PHY chip on the same [[Printed circuit board|PCB]]. On older PCs the [[Communications and networking riser|CNR connector]] Type B carried MII signals.

Network data on the interface is [[Ethernet frame|framed]] using the IEEE [[Ethernet]] standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a [[cyclic redundancy check]] (CRC). The original MII transfers network data using 4-bit [[nibble]]s in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25&nbsp;MHz to achieve {{nowrap|100 Mbit/s}} throughput. The original MII design has been extended to support reduced signals and increased speeds. Current variants include:

* [[#RMII|Reduced media-independent interface]] ('''RMII''')
* [[#GMII|Gigabit media-independent interface]] ('''GMII''')
* [[#RGMII|Reduced gigabit media-independent interface]] ('''RGMII''')
* Serial media-independent interface ('''SMII''')<ref>{{cite web|url=http://ww1.microchip.com/downloads/en/DeviceDoc/KSZ8001L-S-Data-Sheet-DS00003062A.pdf|title=KSZ8001L/S 1.8V, 3.3V 10/100BASE-T/TX/FX Physical Layer Transceiver}}</ref>
* [[#SGMII|Serial gigabit media-independent interface]] ('''serial GMII''', '''SGMII''')
* [[#HSGMII|High serial gigabit media-independent interface]] ('''HSGMII''')
* [[#QSGMII|Quad serial gigabit media-independent interface]] ('''QSGMII''')
* [[#QSGMII|Penta serial gigabit media-independent interface]] ('''PSGMII''')
* [[#XGMII|10-gigabit media-independent interface]] ('''XGMII''')

The [[Management Data Input/Output]] (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using [[autonegotiation]], the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.