Editing Memory barrier (section)

{{Short description|Computer synchronizing instruction}}
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In [[computing]], a '''memory barrier''', also known as a '''membar''', '''memory fence''' or '''fence instruction''', is a type of [[Barrier (computer science)|barrier]] [[Instruction (computer science)|instruction]] that causes a [[central processing unit]] (CPU) or [[compiler]] to enforce an [[Memory ordering|ordering]] constraint on [[Random-access memory|memory]] operations issued before and after the barrier instruction. This typically means that operations issued prior to the barrier are guaranteed to be performed before operations issued after the barrier.

Memory barriers are necessary because most modern CPUs employ performance optimizations that can result in [[out-of-order execution]]. This reordering of memory operations (loads and stores) normally goes unnoticed within a single [[Thread (computing)|thread of execution]], but can cause unpredictable behavior in [[Concurrent computing|concurrent programs]] and [[device driver]]s unless carefully controlled. The exact nature of an ordering constraint is hardware dependent and defined by the architecture's [[memory model (programming)|memory ordering model]]. Some architectures provide multiple barriers for enforcing different ordering constraints.

Memory barriers are typically used when implementing low-level [[machine code]] that operates on memory shared by multiple devices. Such code includes [[Synchronization (computer science)|synchronization]] [[Language primitive|primitives]] and [[Non-blocking synchronization|lock-free]] data structures on [[Multiprocessing|multiprocessor]] systems, and device drivers that communicate with [[computer hardware]].