Editing Nios II (section)

{{Short description|Processor architecture}}
{{other uses of|NIOS|Nios (disambiguation)}}
{{More citations needed|date=July 2018}}
{{Infobox CPU architecture
| name       = Nios II
| designer   = [[Altera]]/[[Intel]]
| bits       = 32-bit
| introduced = 
| version    = 
| design     = RISC
| type       = 
| encoding   =
| branching  = 
| endianness = Little-Endian
| extensions = 
| open       = No
| registers  =
| gpr        = 32
}}

'''Nios II''' is a [[32-bit]] embedded processor architecture designed specifically for the [[Altera]] family of [[field-programmable gate array]] (FPGA) [[Integrated circuit|integrated circuits]]. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from [[digital signal processing]] (DSP) to system-control.

Nios II is a successor to Altera's first configurable [[16-bit]] embedded processor [[Nios embedded processor|Nios]], introduced in 2000.<ref>{{cite web|url=https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pr/nios2_backgrounder.pdf|title=Nios II Embedded Processor Backgrounder|author=Altera}}</ref>

Intel announced the discontinuation of Nios II in 2023, with its successor being [[Nios V]], based on the [[RISC-V]] architecture.<ref>{{Cite web |title=Intel is discontinuing IP ordering codes listed in PDN2312 for Nios® II IP |url=https://www.intel.com/content/www/us/en/content-details/781327/intel-is-discontinuing-ip-ordering-codes-listed-in-pdn2312-for-nios-ii-ip.html |access-date=2025-01-22 |website=Intel}}</ref>