Editing OpenRISC (section)

{{Short description|Microprocessor development project}}
{{Infobox CPU architecture
| name       = OpenRISC
| designer   = Originally Damjan Lampret, now the [https://openrisc.io/community OpenRISC Community] (Stafford Horne etc.)
| bits       = [[32-bit]], [[64-bit]]
| introduced = {{Start date and age|2000}}
| version    = 1.4<ref>{{cite web|url=https://openrisc.io/architecture#published-versions|title=Published versions|access-date=2021-03-28}}</ref>
| design     = [[Reduced instruction set computer|RISC]]
| type       = 
| encoding   = Fixed
| branching  = 
| endianness = Big; unimplemented stub for Little
| page size  = 8 KiB
| extensions = ORFPX32/64,<ref>{{cite web|url=https://openrisc.io/architecture#basic-features|title=Floating point extensions operating on 32-bit/64-bit|access-date=2021-03-28}}</ref> ORVDX64<ref>{{cite web|url=https://openrisc.io/architecture#basic-features|title=Vector/DSP extensions (SIMD) operating on 8-, 16-, 32- and 64-bit data|access-date=2021-03-28}}</ref>
| open       = Yes (LGPL / GPL), hence royalty free
| registers  = 
| gpr        = 16 or 32
| fpr        = Optional
}}

'''OpenRISC''' is a project to develop a series of [[open-source hardware]] based [[central processing unit]]s (CPUs) on established [[reduced instruction set computer]] (RISC) principles. It includes an [[instruction set architecture]] (ISA) using an [[open-source license]]. It is the original flagship project of the [[OpenCores]] community.

The first (and {{as of|2019|lc=y}} only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of [[32-bit]] and [[64-bit]] processors with optional [[floating-point arithmetic]] and [[Vector processor|vector processing]] support.<ref>{{cite web|url=https://openrisc.io/architecture|website=OpenRisc.io|access-date=2021-04-17| title=Architecture - OpenRISC }}</ref>
The [[OpenRISC 1200]] implementation of this specification was designed by Damjan Lampret in 2000, written in the [[Verilog]] [[hardware description language]] (HDL).<ref>{{cite news |last=Clarke |first=Peter |date=2000-02-28 |title=Free 32-bit processor core hits the Net |url=https://www.eetimes.com/document.asp?doc_id=1214097 |work=Electronic Engineering Times ([[EE Times]]) |publisher=AspenCore Media |location=[[San Francisco]], California, United States |access-date=2019-03-21}}</ref> The later mor1kx implementation, which has some advantages compared to the OR 1200,<ref>{{cite web|url=https://openrisc.io/implementations#mor1kx|website=OpenRisc.io|access-date=2021-04-17| title=Implementations - OpenRISC }}</ref> was designed by Julius Baxter and is also written in Verilog. Software simulators also exist<ref>{{cite web|url=https://openrisc.io/implementations#system-simulators|website=OpenRisc.io|access-date=2021-04-17| title=Implementations - OpenRISC }}</ref> which implement the OR1k specification. 

The hardware design was released under the [[GNU Lesser General Public License]] (LGPL), while the models and firmware were released under the [[GNU General Public License]] (GPL).

A reference [[system on a chip]] (SoC) implementation based on the OpenRISC 1200 was developed, named the ''OpenRISC Reference Platform System-on-Chip'' (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on [[field-programmable gate array]]s (FPGAs),<ref>{{cite web |last1=Pelgrims |first1=Patrick |last2=Tierens |first2=Tom |last3=Driessens |first3=Dries |date=2004 |url=http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf |title=Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGAs |version=1.0 |website=De Nayer Instituut |access-date=2009-03-03 |archive-url=https://web.archive.org/web/20061127055325/http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf |archive-date=2006-11-27}}</ref><ref>{{cite thesis |last1=Li |first1=Xiang |last2=Zuo |first2=Lin |title=Open source embedded platform based on OpenRISC and DE2-70 |type=Masters |publisher=[[KTH Royal Institute of Technology]] (KTH), Sweden |url=http://www.olivercamel.com/post/master_thesis.html |archive-url=https://web.archive.org/web/20111006172138/http://www.olivercamel.com/post/master_thesis.html |archive-date=2011-10-06 |url-status=dead }}, SoC program</ref> and there have been several commercial derivatives produced.

Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are minSoC, OpTiMSoC and MiSoC.<ref>{{cite web|url=https://openrisc.io/soc|website=OpenRisc.io|access-date=2021-04-17| title=System-on-Chip - OpenRISC }}</ref>