Editing PRAM consistency (section)

{{Notability|date=February 2024}}
'''PRAM consistency''' (pipelined [[random access memory]]) also known as ''[[FIFO (computing and electronics)|FIFO]] [[Consistency model|consistency]]''.

All [[Process (computing)|processes]] see [[Computer storage|memory]] writes from one process in the order they were issued from the process.<ref>{{cite book|last=Lipton/Sandberg|title=PRAM: a scalable shared memory|year=1988}}</ref> 

Writes from different processes may be seen in a different order on different processes.  Only the write order needs to be [[consistent]], thus the name  ''pipelined''.
PRAM consistency is easy to implement. In effect it says that there are no guarantees about the order in which different processes see writes, except that two or more writes from a single source must arrive in order, as though they were in a pipeline.

   P1:W(x)1 
   P2:       R(x)1W(x)2
   P3:                  R(x)1R(x)2
   P4:                  R(x)2R(x)1
   Time ---->
Fig: A valid sequence of events  for PRAM consistency.

The above sequence is not valid for [[Causal consistency]] because W(x)1 and W(x)2 are causal, so different processes must read it in the same sequence.