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RapidIO
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{{Short description|High-speed interconnect technology}} {{Multiple issues| {{Promotional|date=September 2019}} {{Tone|article|{{subst:September 2022}}|date=September 2022}} }} {{Infobox Computer Hardware Bus |name = RapidIO |image = RapidIO logo fair use.jpg |caption = RapidIO - the unified fabric for Performance Critical Computing |invent-date = {{Start date and age|2000}} |invent-name = |key-persons = |replaces = |width = Port widths of 1, 2, 4, 8, and 16 lanes |speed = Per lane (each direction): *'''1.x''': 1.25, 2.5, 3.125 [[Gigabaud]] *'''2.x''': added 5 and 6.25 Gigabaud *'''3.x''': added 10.3125 Gigabaud *'''4.x''': added 12.5 and 25.3125 Gigabaud |numdev = Sizes of 256, 65,536, and 4,294,967,296 |style = s |hotplug = Yes |external = Yes, Chip-Chip, Board-Board (Backplane), Chassis-Chassis |website = {{URL|www.rapidio.org}} }} The '''RapidIO''' architecture is a high-performance [[packet switching|packet-switched]] [[electrical connection]] technology. It supports messaging, read/write and [[cache coherency]] semantics. Based on industry-standard electrical specifications such as those for [[Ethernet]], RapidIO can be used as a chip-to-chip, board-to-board, and chassis-to-chassis interconnect.
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