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Register-transfer level
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{{Use American English|date = April 2019}} {{Short description|Digital circuit design abstraction}} {{Distinguish|Register transfer language|Resistor–transistor logic}} {{refimprove|date=December 2009}} In [[digital circuit design]], '''register-transfer level''' ('''RTL''') is a design abstraction which models a [[synchronous circuit|synchronous]] [[digital circuit]] in terms of the flow of digital signals ([[data]]) between [[hardware register]]s, and the [[Boolean logic|logical operations]] performed on those signals. Register-transfer-level abstraction is used in [[hardware description language]]s (HDLs) like [[Verilog]] and [[VHDL]] to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design.<ref> {{cite book | title = Digital Design with RTL Design, Verilog and VHDL | edition = 2nd | author = Frank Vahid | publisher = John Wiley and Sons | year = 2010 | isbn = 978-0-470-53108-2 | page = 247 | url = https://books.google.com/books?id=-YayRpmjc20C&pg=PA247 }}</ref> Unlike in software compiler design, where the register-transfer level is an intermediate representation and at the lowest level, the RTL level is the usual input that circuit designers operate on. In circuit synthesis, an intermediate language between the input register transfer level representation and the target [[netlist]] is sometimes used. Unlike in netlist, constructs such as cells, functions, and multi-bit registers are available.<ref>[https://yosys.readthedocs.io/_/downloads/en/latest/pdf/ Yosys Manual] (RTLIL)</ref> Examples include FIRRTL and RTLIL. [[Transaction-level modeling]] is a higher level of [[Electronic design automation|electronic system design]].
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