Editing SSE3 (section)

{{Short description|CPU instruction set}}
{{Distinguish|SSSE3}}
'''SSE3''', '''Streaming SIMD Extensions 3''', also known by its [[Intel]] code name '''Prescott New Instructions''' ('''PNI'''),<ref name=":1">{{Cite web |last1=Shimpi |first1=Anand Lal |last2=Wilson |first2=Derek |title=Intel's Pentium 4 E: Prescott Arrives with Luggage |url=https://www.anandtech.com/show/1230 |access-date=2023-04-10 |website=www.anandtech.com}}</ref> is the third iteration of the [[Streaming SIMD Extensions|SSE]] instruction set for the [[IA-32]] (x86) architecture. Intel introduced SSE3 in early 2004 with the [[Pentium 4#Prescott|Prescott]] revision of their [[Pentium 4]] CPU.<ref name=":1" /> In April 2005, [[AMD]] introduced a subset of SSE3 in revision E (Venice and San Diego) of their [[Athlon 64]] CPUs.<ref>{{Cite web |last=Shimpi |first=Anand Lal |title=Industry Update - Q4-2004: AMD adds SSE3 Support, Intel's 925/915 not selling and more |url=https://www.anandtech.com/show/1532 |access-date=2023-04-10 |website=www.anandtech.com}}</ref> The earlier [[SIMD]] instruction sets on the [[x86]] platform, from oldest to newest, are [[MMX (instruction set)|MMX]], [[3DNow!]] (developed by AMD, no longer supported on newer CPUs), [[Streaming SIMD Extensions|SSE]], and [[SSE2]].

SSE3 contains 13 new instructions over [[SSE2]].<ref>{{Cite web |title=Intel Instruction Set Extensions Technology |url=https://www.intel.com/content/www/us/en/support/articles/000005779/processors.html |access-date=2023-04-10 |website=Intel |language=en}}</ref>