Editing Serial communication (section)

{{short description|Type of data transfer}}
{{more citations needed|date=August 2019}}
{{Use American English|date=May 2024}}

[[Image:Serial and Parallel Data Transmission.svg|class=skin-invert-image|thumb|right|300px|Serial and parallel data transmission of 01001011<sub>2</sub>. Standard bit sequence is least-significant-bit-first (D<sub>0</sub> to D<sub>7</sub> in ascending order).<ref name="Mackenzie_1980">{{cite book |url=https://textfiles.meulie.net/bitsaved/Books/Mackenzie_CodedCharSets.pdf |title=Coded Character Sets, History and Development |series=The Systems Programming Series |author-last=Mackenzie |author-first=Charles E. |date=1980 |edition=1 |publisher=[[Addison-Wesley Publishing Company, Inc.]] |isbn=978-0-201-14460-4 |lccn=77-90165 |pages=247–253 |access-date=2022-12-29 |archive-url=https://web.archive.org/web/20160526172151/https://textfiles.meulie.net/bitsaved/Books/Mackenzie_CodedCharSets.pdf |archive-date=May 26, 2016 |url-status=live |df=mdy-all }}</ref> D<sub>0</sub> is received first via serial transmission. All bits are received simultaneously via parallel transmission.]]

In [[telecommunication]] and [[data transmission]], '''serial communication''' is the process of sending [[data]] one [[bit]] at a time, sequentially, over a [[communication channel]] or [[computer bus]]. This is in contrast to [[parallel communication]], where several bits are sent as a whole, on a link with several parallel channels.

[[Image:MIL-STD-188-100 char struct for async comms 1972-11-15.svg|class=skin-invert-image|thumb|right|400px|Standard character structure for asynchronous data communication consisting of 10 elements for a 7-bit ASCII character]]
Serial communication is used for all [[Long-haul communications|long-haul communication]] and most [[computer network]]s, where the cost of [[electrical cable|cable]] and difficulty of [[synchronization]] make parallel communication impractical. Serial computer buses have become more common even at shorter distances, as improved [[signal integrity]] and transmission speeds in newer serial technologies have begun to outweigh the parallel bus's advantage of simplicity (no need for serializer and deserializer, or [[SerDes]]) and to outstrip its disadvantages ([[clock skew]], interconnect density). The migration from [[Peripheral Component Interconnect|PCI]] to [[PCI Express]] (PCIe) is an example.

Modern high speed serial interfaces such as PCIe<ref>{{cite web |url=https://www.theregister.com/2022/01/12/final_pcie_60_specs_released/ |title=Final PCIe 6.0 specs unleashed: 64 GTps link speed incoming... with products to follow in 2023 |first=Dan |last=Robinson |date=12 January 2022 |website=[[The Register]]}}</ref><ref>{{cite web | url=https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | title=PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025 }}</ref><ref>{{cite web | url=https://arstechnica.com/gadgets/2022/01/pci-express-6-0-spec-is-finalized-doubling-bandwidth-for-ssds-gpus-and-more/ | title=PCIe 5.0 is just beginning to come to new PCS, but version 6.0 is already here | date=12 January 2022 }}</ref>  send data several bits at a time using modulation/encoding techniques such as [[PAM4]] which groups 2 bits at a time into a single symbol, and several symbols are still sent one at the time. This replaces PAM2 or non return to zero (NRZ) which only sends one bit at a time, or in other words one bit per symbol.<ref>{{cite book | url=https://books.google.com/books?id=wnGDBAAAQBAJ&dq=serial+pam4+signals&pg=PA9 | isbn=978-0-12-800671-9 | title=Handbook of Serial Communications Interfaces: A Comprehensive Compendium of Serial Digital Input/Output (I/O) Standards | date=21 August 2015 | publisher=Newnes }}</ref><ref>{{cite web | url=https://www.signalintegrityjournal.com/articles/1151-pam4-for-better-and-worse | title=PAM4: For Better and Worse &#124; 2019-02-26 &#124; Signal Integrity Journal }}</ref><ref>{{cite web | url=https://semiengineering.com/knowledge_centers/communications-io/off-chip-communications/pam-4-signaling/ | title=PAM-4 Signaling }}</ref><ref>{{cite conference |url=https://www.xilinx.com/publications/events/designcon/2016/slides-pam4signalingfor56gserial-zhang-designcon.pdf |title=PAM4 Signaling for 56G Serial Link Applications − A Tutorial |first1=Hongtao |last1=Zhang |first2=Brandon |last2=Jiao |first3=Yu |last3=Liao |first4=Geoff |last4=Zhang |conference=DesignCon 2016}}</ref><ref>{{cite web |url=https://download.tek.com/document/PAM4-Signaling-in-High-Speed-Serial-Technology_55W-60273.pdf |title=PAM4 Signaling in High-Speed Serial Technology: Test, Analysis, and Debug |type=application note |publisher=[[Tektronix]]}}</ref><ref>{{cite book | url=https://books.google.com/books?id=JljBDwAAQBAJ&dq=pam4+symbol&pg=PA54 | isbn=978-3-03921-792-2 | title=Advanced DSP Techniques for High-Capacity and Energy-Efficient Optical Fiber Communications | date=3 December 2019 | last1=Pan | first1=Zhongqi | last2=Yue | first2=Yang }}</ref><ref>{{cite book | url=https://books.google.com/books?id=MlruDwAAQBAJ&dq=pam4+symbol&pg=PA944 | isbn=978-1-119-52149-5 | title=Essentials of Modern Communications | date=4 August 2020 | publisher=John Wiley & Sons }}</ref><ref>{{cite journal |url=https://www.researchgate.net/figure/Eye-diagrams-of-PAM-2-4-8-with-normalized-vertical-full-swing-level-Peak-to-peak-swings_fig2_361960252 |title=Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications |first=Gain |last=Kim |at=Figure 2 |journal=IEEE Open Journal of Circuits and Systems |issn=2644-1225 |volume=3 |issue=1 |date=January 2022 |doi=10.1109/OJCAS.2022.3189550|doi-access=free }}</ref> The symbols are sent at a speed known as the symbol rate or the baud rate.<ref>{{cite web | url=https://www.edn.com/eye-diagrams-the-tool-for-serial-data-analysis/ | title=Eye diagrams: The tool for serial data analysis | date=4 June 2019 }}</ref><ref>{{cite web | url=https://www.rfwireless-world.com/Terminology/Advantages-and-disadvantages-of-PAM4-modulation.html | title=Advantages of PAM4 modulation &#124; Disadvantages PAM4 signaling }}</ref><ref>{{cite web | url=https://www.edn.com/generate-pam4-signals-for-receiver-compliance-testing/ | title=Generate PAM4 signals for receiver compliance testing | date=20 September 2016 }}</ref><ref>{{cite book | url=https://books.google.com/books?id=L1YIEQAAQBAJ&dq=pam4+symbol+rate&pg=PA16 | isbn=978-1-040-01179-9 | title=Complex Digital Hardware Design | date=9 May 2024 | publisher=CRC Press }}</ref>