Editing Streaming SIMD Extensions (section)

{{Short description|Computer chip instruction set extension}}
{{More citations needed|date=June 2014}}

In [[computing]], '''Streaming SIMD Extensions''' ('''SSE''') is a single instruction, multiple data ([[SIMD]]) [[instruction set]] extension to the [[x86]] architecture, designed by [[Intel]] and introduced in 1999 in its [[Pentium III]] series of [[central processing unit]]s (CPUs) shortly after the appearance of [[Advanced Micro Devices]] (AMD's) [[3DNow!]]. SSE contains 70 new instructions (65 unique mnemonics<ref>{{cite web
| url=https://cdrdv2.intel.com/v1/dl/getContent/671200
| title=Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture
| date=April 2022
| publisher=Intel
| pages=((5{{hyphen}}16{{ndash}}5{{hyphen}}19))
| access-date=May 16, 2022
| archive-date=April 25, 2022
| archive-url=https://web.archive.org/web/20220425144301/https://cdrdv2.intel.com/v1/dl/getContent/671200
| url-status=live
}}</ref> using 70 encodings), most of which work on [[single precision]] [[floating-point]] data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are [[digital signal processing]] and [[graphics processing]].

Intel's first [[IA-32]] SIMD effort was the [[MMX (instruction set)|MMX]] instruction set. MMX had two main problems: it re-used existing [[x87]] floating-point registers making the CPUs unable to work on both floating-point and SIMD data at the same time, and it only worked on [[integers]]. SSE floating-point instructions operate on a new independent register set, the XMM registers, and adds a few integer instructions that work on MMX registers.

SSE was subsequently expanded by Intel to [[SSE2]], [[SSE3]], [[SSSE3]] and [[SSE4]]. Because it supports floating-point math, it had wider applications than MMX and became more popular. The addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations{{when|date=November 2017}} by using MMX in parallel with SSE operations.

SSE was originally called '''Katmai New Instructions''' ('''KNI'''), [[Katmai (microprocessor)|Katmai]] being the code name for the first Pentium III core revision. During the Katmai project Intel sought to distinguish it from its earlier product line, particularly its flagship [[Pentium II]]. It was later renamed '''Internet Streaming SIMD Extensions''' ('''ISSE'''<ref name="MPR=1999-03-08"/>), then SSE. 

AMD added a subset of SSE, 19 of them, called new MMX instructions,<ref name="extman">{{cite web|url=https://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf|title=AMD Extensions to the 3DNow and MMX Instruction Sets Manual|publisher=[[Advanced Micro Devices, Inc.]]|date=March 2000|access-date=2024-04-18|archive-date=2008-05-17|archive-url=https://web.archive.org/web/20080517014932/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf|url-status=dead}}</ref> and known as several variants and combinations of SSE and MMX, shortly after with the release of the original [[Athlon]] in August 1999, see [[3DNow!#3DNow!_extensions|3DNow! extensions]]. AMD eventually added full support for SSE instructions, starting with its [[Athlon XP]] and [[Duron]] ([[Duron#Morgan (Model 7, 180 nm)|Morgan core]]) processors.