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Sum-addressed decoder
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{{Multiple issues| {{More citations needed|date=June 2019}} {{More footnotes|date=April 2022}} }} In [[CPU design]], the use of a '''sum-addressed decoder (SAD)''' or '''sum-addressed memory (SAM) decoder''' is a method of reducing the latency of the [[CPU cache]] access and address calculation (base + offset). This is achieved by fusing the address generation sum operation with the decode operation in the cache [[Static random access memory|SRAM]].
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