Editing Superscalar processor (section)

{{short description|CPU that implements instruction-level parallelism within a single processor}}
{{Redirect|Superscaler|the Sega arcade system board|Sega Super Scaler}}
{{more footnotes|date=October 2017}}
[[File:Superscalarpipeline.svg|thumb|Simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per cycle can be completed. (IF = instruction fetch, ID = instruction decode, EX = execute, MEM = memory access, WB = register write-back, ''i'' = instruction number, ''t'' = clock cycle [i.e. time])]]
[[File:Processor board cray-2 hg.jpg|thumb|Processor board of a [[Cray T3E|CRAY T3e]] supercomputer with four ''superscalar'' [[Alpha 21164]] processors]]

A '''superscalar processor''' (or '''multiple-issue processor'''<ref>P. Pacheco, ''Introduction to Parallel Programming'', 2011, section 2.2.5, "There are two main approaches to ILP: pipelining ... and multiple issue ... A processor that supports dynamic multiple issue is
sometimes said to be superscalar." [[Andrew A. Chien|A. Chien]], ''Computer Architecture for Scientists'', 2022, page 102, "multiple-issue (aka superscalar)".</ref>) is a [[Central processing unit|CPU]] that implements a form of [[Parallel computer|parallelism]] called [[instruction-level parallelism]] within a single processor.<ref>{{Cite web |title=What is a Superscalar Processor? - Definition from Techopedia |url=http://www.techopedia.com/definition/2897/superscalar-processor |access-date=2022-08-29 |website=Techopedia.com |date=28 February 2019 |language=en}}</ref> In contrast to a [[scalar processor]], which can execute at most one single instruction per clock cycle, a superscalar processor can execute or start executing more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different [[execution unit]]s on the processor. It therefore allows more [[throughput]] (the number of instructions that can be executed in a unit of time which can even be less than 1) than would otherwise be possible at a given [[clock rate]]. Each execution unit is not a separate processor (or a core if the processor is a [[multi-core processor]]), but an execution resource within a single CPU such as an [[arithmetic logic unit]].

While a superscalar CPU is typically also [[instruction pipeline|pipelined]], superscalar and pipelining execution are considered different performance enhancement techniques. The former (superscalar) executes multiple instructions in parallel by using multiple execution units, whereas the latter (pipeline) executes multiple instructions in the same execution unit in parallel by dividing the execution unit into different phases.  In the "Simple superscalar pipeline" figure, fetching two instructions at the same time is superscaling, and fetching the next two before the first pair has been written back is pipelining.

The superscalar technique is traditionally associated with several identifying characteristics (within a given CPU):
* Instructions are issued from a sequential instruction stream
* The CPU dynamically checks for [[data dependencies]] between instructions at run time (versus software checking at [[compile time]])
* The CPU can execute multiple instructions per clock cycle