Editing Synchronous dynamic random-access memory (section)

{{Short description|Type of computer memory}}
{{redirect|PC100|the Japanese home computer|NEC PC-100}}
{{Memory types}}
[[File:SDRAM_memory_module.jpg|thumb|SDRAM memory module]]
'''Synchronous dynamic random-access memory''' ('''synchronous dynamic RAM''' or '''SDRAM''') is any [[Dynamic random-access memory|DRAM]] where the operation of its external pin interface is coordinated by an externally supplied [[clock signal]].

DRAM [[integrated circuit]]s (ICs) produced from the early 1970s to the early 1990s used an ''asynchronous'' interface, in which input control signals have a direct effect on internal functions delayed only by the trip across its semiconductor pathways. SDRAM has a ''synchronous'' interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by [[JEDEC]], the clock signal controls the stepping of an internal [[finite-state machine]] that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called ''[[Memory bank|bank]]s'', allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an [[Interleaved memory|interleaved]] fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.

[[Pipeline (computing)|Pipelining]] means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.