Editing SystemC (section)

{{Use American English|date = March 2019}}
{{Short description|C++ extensions for simulating embedded systems}}
{{Use mdy dates|date = March 2019}}
{{for|the UK health care company|System C}}
'''SystemC''' is a set of [[C++]] classes and macros which provide an [[event-driven programming|event-driven]] simulation interface (see also [[discrete event simulation]]).  These facilities enable a designer to ''simulate'' [[concurrent process]]es, each described using plain [[C++]] [[syntax]]. SystemC processes can communicate in a ''simulated'' real-time environment, using signals of all the [[datatype]]s offered by C++, some additional ones offered by the SystemC library, as well as user defined. In certain respects, SystemC deliberately mimics the [[hardware description language]]s [[VHDL]] and [[Verilog]], but is more aptly described as a ''system-level modeling language''.

SystemC is applied to system-level [[scientific modelling|model]]ing, architectural exploration, performance modeling, [[software development]], [[functional verification]], and [[high-level synthesis]]. SystemC is often associated with [[electronic system-level]] (ESL) design, and with [[transaction-level modeling]] (TLM).