Editing Translation lookaside buffer (section)

{{Short description|Computer component}}
{{Use dmy dates|date=September 2019}}
A '''translation lookaside buffer''' ('''TLB''') is a memory [[CPU cache|cache]] that stores the recent translations of [[virtual memory]] to [[physical memory]]. It is used to reduce the time taken to access a user memory location.<ref name="ostep-1">{{citation |last1=Arpaci-Dusseau |first1=Remzi H. |title=Operating Systems: Three Easy Pieces [Chapter: Faster Translations (TLBs)] |date=2014 |url=http://pages.cs.wisc.edu/~remzi/OSTEP/vm-tlbs.pdf |publisher=Arpaci-Dusseau Books |last2=Arpaci-Dusseau |first2=Andrea C.}}</ref> It can be called an address-translation cache.  It is a part of the chip's [[Memory management unit|memory-management unit]] (MMU). A TLB may reside between the [[Central processing unit|CPU]] and the [[CPU cache]], between CPU cache and the main memory or between the different levels of the multi-level cache. The majority of desktop, laptop, and server processors include one or more TLBs in the memory-management hardware, and it is nearly always present in any processor that uses [[Memory paging|paged]] or [[Memory segmentation|segmented]] [[virtual memory]].

The TLB is sometimes implemented as [[content-addressable memory]] (CAM). The CAM search key is the virtual address, and the search result is a [[physical address]]. If the requested address is present in the TLB, the CAM search yields a match quickly and the retrieved physical address can be used to access memory. This is called a TLB hit. If the requested address is not in the TLB, it is a miss, and the translation proceeds by looking up the [[page table]] in a process called a ''page walk''. The page walk is time-consuming when compared to the processor speed, as it involves reading the contents of multiple memory locations and using them to compute the physical address. After the physical address is determined by the page walk, the virtual address to physical address mapping is entered into the TLB.  The [[PowerPC 604]], for example, has a two-way [[set-associative]] TLB for data loads and stores.<ref>{{cite journal|url=http://users.ece.gatech.edu/~scotty/7102/PPC604.pdf|title=The PowerPC 604 RISC Microprocessor|author1=S. Peter Song|author2=Marvin Denman|author3=Joe Chang|journal=IEEE Micro|volume=14|issue=5|date=October 1994|pages=13–14|doi=10.1109/MM.1994.363071|s2cid=11603864 |archive-url=https://web.archive.org/web/20160601135015/http://users.ece.gatech.edu/~scotty/7102/PPC604.pdf|archive-date=2016-06-01|url-status=dead}}</ref> Some processors have different instruction and data address TLBs.