Open main menu
Home
Random
Recent changes
Special pages
Community portal
Preferences
About Wikipedia
Disclaimers
Incubator escapee wiki
Search
User menu
Talk
Dark mode
Contributions
Create account
Log in
Editing
VIA C7
(section)
Warning:
You are not logged in. Your IP address will be publicly visible if you make any edits. If you
log in
or
create an account
, your edits will be attributed to your username, along with other benefits.
Anti-spam check. Do
not
fill this in!
{{Short description|Central processing unit designed by Centaur Technology and sold by VIA Technologies}}{{Infobox CPU | name = C7 | image = KL_VIA_C7_M.jpg | caption = C7-M 795 2.0 GHz | produced-start = May 2005 | slowest = 1.0 | slow-unit = GHz | fastest = 2.0 | fast-unit = GHz | fsb-slowest = 400 | fsb-slow-unit = MT/s | fsb-fastest = 800 | fsb-fast-unit = MT/s | l1cache = 64 KiB instruction + 64 KiB data | l2cache = 128 KiB 32-way exclusive | size-from = 90nm | manuf1 = VIA Technologies | numcores = 1 | core1 = Esther (C5J) | sock1 = [[Socket 479]] | sock2 = nanoBGA2 400 | arch = [[x86-16]], [[IA-32]] | extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[VIA_PadLock|PadLock]] (AES, RNG, SHA, PMM) | predecessor = [[VIA C3]] | successor = [[VIA Nano]] }} The '''VIA C7''' is an [[x86]] [[central processing unit]] designed by [[Centaur Technology]] and sold by [[VIA Technologies]].
Edit summary
(Briefly describe your changes)
By publishing changes, you agree to the
Terms of Use
, and you irrevocably agree to release your contribution under the
CC BY-SA 4.0 License
and the
GFDL
. You agree that a hyperlink or URL is sufficient attribution under the Creative Commons license.
Cancel
Editing help
(opens in new window)