Editing Verilog (section)

{{Short description|Hardware description language}}
{{Use American English|date = April 2019}}
{{Use dmy dates|date=January 2021}}
{{Infobox programming language
| name = Verilog
| logo = 
| logo caption = 
| screenshot = 
| screenshot caption = 
| file ext = .v, [[header file|.vh]]
| paradigm = [[structured programming|Structured]]
| released = {{Start date|1984}}
| designer = [[Prabhu Goel]], [[Phil Moorby]] and Chi-Lai Huang
| developer = [[IEEE]]
| discontinued = Merged into [[SystemVerilog]]
| latest release version = IEEE 1800-2023
| latest release date = {{start date and age|df=yes|2023|12|6}}
| latest preview version = 
| latest preview date = <!-- {{start date and age|YYYY|MM|DD}} -->
| typing = [[Type system|Static]], [[Weak typing|weak]]
| implementations = 
| dialects = [[Verilog-AMS]]
| influenced by = [[Pascal (programming language)|Pascal]], [[Ada (programming language)|Ada]], [[C (programming language)|C]], [[Fortran]]
| influenced = [[SystemVerilog]]
| programming language = 
| platform = 
| operating system = 
| license = 
| website = https://ieeexplore.ieee.org/document/10458102
| wikibooks = Programmable Logic/Verilog
}}
'''Verilog''', [[standardized]] as '''IEEE 1364''', is a [[hardware description language]] (HDL) used to model [[electronic system]]s. It is most commonly used in the design and verification of digital circuits, with the highest level of abstraction being at the [[register-transfer level]]. It is also used in the verification of [[Analogue electronics|analog circuits]] and [[Mixed-signal integrated circuit|mixed-signal circuits]], as well as in the design of [[Synthetic biological circuit|genetic circuits]].<ref>{{cite journal |vauthors=Nielsen AA, Der BS, Shin J, Vaidyanathan P, Paralanov V, Strychalski EA, Ross D, Densmore D, Voigt CA |title=Genetic circuit design automation |journal=Science |volume=352 |issue=6281 |pages=aac7341 |year=2016 |pmid=27034378 |doi=10.1126/science.aac7341 |doi-access=free }}</ref>

In 2009, the Verilog standard (IEEE 1364-2005) was merged into the [[SystemVerilog]] standard, creating IEEE Standard 1800-2009. Since then, Verilog has been officially part of the SystemVerilog language. The current version is IEEE standard 1800-2023.<ref name="IEEE2023" />