Editing Xeon (section)

{{short description|Line of Intel server and workstation processors}}
{{distinguish|Xenon|Intel Xe}}
{{for|the English music producer|Sophie (musician)}}
{{Use mdy dates|date=October 2018}}
{{Infobox CPU
| name           = Xeon
| image          = Intel-Xeon-Badge-2024.jpg
| image_size     = 
| alt            = 
| caption        = Logo since 2024
<!----------------- General Info ----------------->
| produced-start = {{Start date and age|June 1998}}
| produced-end   = 
| soldby         = [[Intel]]
| designfirm     = Intel
| manuf1         = Intel
| cpuid          = 
| code           = 
<!----------------- Performance ------------------>
| slowest        = 400
| slow-unit      = MHz
| fastest        = 5.3
| fast-unit      = GHz
| fsb-slowest    = 100
| fsb-fastest    = 1.6
| fsb-slow-unit  = MT/s
| fsb-fast-unit  = GT/s
| hypertransport-slowest   = 
| hypertransport-fastest   = 
| hypertransport-slow-unit = 
| hypertransport-fast-unit = 
| qpi-slowest    = 4.8
| qpi-fastest    = 24
| qpi-slow-unit  = GT/s
| qpi-fast-unit  = GT/s
| dmi-slowest    = 2.0
| dmi-fastest    = 16
| dmi-slow-unit  = GT/s
| dmi-fast-unit  = GT/s
| data-width     = Up to 64 bits
| address-width  = Up to 64 bits
| virtual-width  = Up to 57 bits
<!-------------------- Cache --------------------->
| l1cache        = Up to 80&nbsp;KB per core <!-- leave it 80kb and don't change it to 112kb until granite rapids comes -->
| l2cache        = Up to 2&nbsp;MB per core
| l3cache        = Up to 320&nbsp;MB per socket <!-- leave it 320mb and don't change it to 480mb until granite rapids comes -->
| l4cache        = Up to 64{{nbsp}}GB [[High Bandwidth Memory#HBM2E|HBM2e]]<ref>{{cite web |last1=Cutress |first1=Ian |date=November 15, 2021 |title=Intel: Sapphire Rapids With 64 GB of HBM2e, Ponte Vecchio with 408 MB L2 Cache |url=https://www.anandtech.com/show/17067/intel-sapphire-rapids-with-64-gb-of-hbm2e-ponte-vecchio-with-408-mb-l2-cache |website=AnandTech |language=en-US |access-date=December 11, 2022}}</ref>
| llcache        = 
<!------- Architecture and classification -------->
| application    = {{ubl
  |[[Server (computing)|Servers]]
  |[[Workstation|Workstations]]
  |[[Embedded system|Embedded systems]]
}}
| size-from      = 250 nm
| size-to        = Intel 3 and TSMC N5
| microarch      = {{Unbulleted list
  | [[P6 (microarchitecture)|P6]]
  | [[NetBurst]]
  | [[Intel Core (microarchitecture)|Core]]
  | [[Nehalem (microarchitecture)|Nehalem]]
  | [[Westmere (microarchitecture)|Westmere]]
  | [[Sandy Bridge]]
  | [[Ivy Bridge (microarchitecture)|Ivy Bridge]]
  | [[Haswell (microarchitecture)|Haswell]]
  | [[Broadwell (microarchitecture)|Broadwell]]
  | [[Skylake (microarchitecture)|Skylake]]
  | [[Sunny Cove (microarchitecture)|Sunny Cove]]
  | [[Cypress Cove (microarchitecture)|Cypress Cove]]
  | [[Golden Cove (microarchitecture)|Golden Cove]]
  | [[Golden Cove (microarchitecture)#Raptor Cove|Raptor Cove]]
  | [[Redwood Cove (microarchitecture)|Redwood Cove]]
  | [[Crestmont (microarchitecture)|Crestmont]]
}}
| arch           = [[x86-16]], [[IA-32]], [[x86-64]]
| instructions   = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE4.1]], [[SSE4.2]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions#Advanced Vector Extensions 2|AVX2]], [[FMA3]], [[AVX-512]], [[Advanced Vector Extensions#AVX-VNNI|AVX-VNNI]], [[Advanced Matrix Extensions|AMX]], [[Transactional Synchronization Extensions|TSX]], [[AES instruction set|AES-NI]], [[CLMUL instruction set|CLMUL]], [[RDRAND]]
| extensions     = [[Intel Software Guard Extensions|SGX]], [[Intel SHA extensions|SHA]], [[Trusted Execution Technology|TXT]], [[VT-x]], [[VT-d]]
<!----------- Physical specifications ------------>
| transistors    =
| numcores       = Up to 64 cores per socket (up to 128 threads per socket)
| amountmemory   = Up to 4&nbsp;TB and 8 channels per socket
| memory1        = Up to [[DDR5]]-5600 with [[Error correction code|ECC]] support
| gpu            = [[Intel Graphics Technology]] (some models only) 
| co-processor   = [[Xeon Phi]] (2010–2020)
| pack1          = 
| sock1          = {{ubl |[[Slot 2]] |[[Socket 603]] |[[Socket 604]] |[[LGA 775]] |[[LGA 771]] |[[LGA 1156]] |[[LGA 1366]] |[[LGA 1155]] |[[LGA 2011]] |[[LGA 1150]] |[[LGA 2011|LGA 2011-3]] |[[LGA 1151]] |[[LGA 1151|LGA 1151v2]] |[[LGA 1200]] |[[LGA 1700]] |[[LGA 2066]] |[[LGA 3647]] |[[LGA 4189]] |[[LGA 4677]]|[[LGA 7529]]}}
<!--------- Products, models, variants ----------->
| core1          = 
| pcode1         = 
| model1         = 
| brand1         = {{ubl |Xeon E |Xeon D |Xeon w3<ref name="Xeon W series">{{cite web |title=Intel Launches New Xeon Workstation Processors – the Ultimate Solution for Professionals |url=https://www.intel.com/content/www/us/en/newsroom/news/intel-launches-new-xeon-workstation-processors.html#gs.qeb2cq |website=Intel |access-date=18 February 2023 |language=en}}</ref>|Xeon w5<ref name="Xeon W series" />|Xeon w7<ref name="Xeon W series" />| Xeon w9<ref name="Xeon W series" />|Xeon Bronze |Xeon Silver |Xeon Gold |Xeon Platinum |Xeon Max<ref>{{cite web |title=Intel Max Series Brings Breakthrough Memory Bandwidth and Performance to HPC and AI |url=https://www.intel.com/content/www/us/en/newsroom/news/introducing-intel-max-series-product-family.html#gs.l5ms7r |website=Intel Newsroom |language=en-US |date=November 9, 2022 |access-date=December 22, 2022}}</ref>}}
| variant        = [[Itanium]] (2001–2020)
<!------------------  History  ------------------->
| predecessor    = [[Pentium Pro]]
| successor      = 
| support status = Supported
}}

'''Xeon''' ({{IPAc-en|ˈ|z|iː|ɒ|n}}; {{respell|ZEE|on}}) is a brand of [[x86]] [[microprocessor]]s designed, manufactured, and marketed by [[Intel]], targeted at the non-consumer [[workstation]], [[Server (computing)|server]], and [[embedded system|embedded]] markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for [[ECC memory|error correction code (ECC) memory]], higher [[Multi-core processor|core]] counts, more [[PCI Express]] lanes, support for larger amounts of RAM, larger [[cache memory]] and extra provision for enterprise-grade [[reliability, availability and serviceability]] (RAS) features responsible for handling hardware exceptions through the [[Machine Check Architecture]] (MCA). They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the [[machine-check exception]] (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the [[Intel Ultra Path Interconnect|Ultra Path Interconnect]] (UPI) bus, which replaced the older [[Intel QuickPath Interconnect|QuickPath Interconnect]] (QPI) bus.
[[File:Intel Xeon E5-1620, front and back.jpg|thumb|center|Intel Xeon E5-1620's front and back]]