Editing 90 nm process (section)

==History==
A 90{{nbsp}}nm [[silicon]] [[MOSFET]] was [[semiconductor device fabrication|fabricated]] by Iranian engineer [[Ghavam Shahidi]] (later [[IBM]] director) with D.A. Antoniadis and H.I. Smith at [[MIT]] in 1988. The device was fabricated using [[X-ray lithography]].<ref>{{cite journal |last1=Shahidi |first1=Ghavam G. |last2=Antoniadis |first2=D. A. |last3=Smith |first3=H. I. |title=Reduction of hot-electron-generated substrate current in sub-100-nm channel length Si MOSFET's |journal=IEEE Transactions on Electron Devices |date=December 1988 |volume=35 |issue=12 |pages=2430– |doi=10.1109/16.8835|bibcode=1988ITED...35.2430S }}</ref>

Toshiba, Sony and Samsung developed a 90{{nbsp}}nm process during 2001{{ndash}}2002, before being introduced in 2002 for Toshiba's [[eDRAM]] and Samsung's 2{{nbsp}}[[Gibibit|Gb]] [[NAND flash]] memory.<ref>{{cite news |title=Toshiba and Sony Make Major Advances in Semiconductor Process Technologies |url=https://www.toshiba.co.jp/about/press/2002_12/pr0301.htm |access-date=26 June 2019 |work=[[Toshiba]] |date=3 December 2002}}</ref><ref name="samsung2000s">{{cite web |title=Our Proud Heritage from 2000 to 2009 |url=https://www.samsung.com/semiconductor/about-us/history-03/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref> IBM demonstrated a 90{{nbsp}}nm [[silicon-on-insulator]] (SOI) [[CMOS]] process, with development led by Shahidi, in 2002. The same year, Intel demonstrated a 90{{nbsp}}nm [[strained-silicon]] process.<ref>{{cite news |title=IBM, Intel wrangle at 90 nm |url=https://www.eetimes.com/document.asp?doc_id=1145379 |access-date=17 September 2019 |work=[[EE Times]] |date=13 December 2002}}</ref> Fujitsu commercially introduced its 90{{nbsp}}nm process in 2003<ref name="fujitsu">{{Cite web |url=http://www.fujitsu.com/downloads/MICRO/fma/pr/PressKit/65nmProcessTechnology.pdf |title=65nm CMOS Process Technology |access-date=20 June 2019 |archive-date=16 May 2020 |archive-url=https://web.archive.org/web/20200516015827/https://www.fujitsu.com/downloads/MICRO/fma/pr/PressKit/65nmProcessTechnology.pdf |url-status=dead }}</ref> followed by TSMC in 2004.<ref>{{cite web |title=90nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/90nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>

[[Gurtej Sandhu|Gurtej Singh Sandhu]] of Micron Technology initiated the development of [[atomic layer deposition]] high-k [[Thin film|films]] for [[Dynamic random-access memory|DRAM]] memory devices. This helped drive cost-effective implementation of [[semiconductor memory]], starting with 90{{nbsp}}nm [[Semiconductor node|node]] DRAM.<ref name="ieee">{{cite web |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |archive-url=https://web.archive.org/web/20180909112404/https://www.ieee.org/about/awards/bios/grove-recipients.html |url-status=dead |archive-date=9 September 2018 |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=4 July 2019}}</ref> 

Intel's 90nm process has a transistor density of 1.45 million transistors per square millimeter (MTr/mm2).<ref>{{cite web | url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3 | title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review }}</ref>