Editing A20 line (section)

== Overview ==
{{See also|x86 memory segmentation}}
The [[Intel 8086]], [[Intel 8088]], and [[Intel 80186]] processors had 20 address lines, numbered A0 to A19; with these, the processor can access 2<sup>20</sup> bytes, or 1&nbsp;MB. Internal address registers of such processors only had 16 bits. To access a 20-bit address space, an external memory reference was made up of a 16-bit ''offset'' address added to a 16-bit ''segment'' number, shifted 4 bits to the left so as to produce a 20-bit physical address. The resulting address is equal to ''segment''&nbsp;× 16&nbsp;+ ''offset''.<ref name="Paul_2002_HMA"/> There are many combinations of segment and offset that produce the same 20-bit physical address. Therefore, there were various ways to address the same byte in memory.<ref name="Paul_2002_SEGOFS"/> For example, here are four of the 4096 different segment:offset combinations, all referencing the byte whose physical address is {{mono|0x000FFFFF}} (the last byte in 1&nbsp;MB-memory space):

: {{mono|F000:FFFF}}
: {{mono|FFFF:000F}}
: {{mono|F555:AAAF}}
: {{mono|F800:7FFF}}

Referenced the last way, an increase of one in the offset yields {{mono|F800:8000}}, which is a proper address for the processor, but since it translates to the physical address {{mono|0x00100000}} (the first byte over 1&nbsp;MB), the processor would need another address line for actual access to that byte. Since there is no such line on the 8086 line of processors, the 21st bit above, while set, gets dropped, causing the address {{mono|F800:8000}} to "wrap around"<ref name="Paul_2002_HMA"/> and to actually point to the physical address {{mono|0x00000000}}.

When [[IBM]] designed the [[IBM PC AT]] (1984) machine, it decided to use the new higher-performance [[Intel 80286]] microprocessor. The 80286 could address up to 16&nbsp;MB of system memory in [[protected mode]]. However, the CPU was supposed to emulate an 8086's behavior in [[real mode]], its startup mode, so that it could run operating systems and programs that were not written for protected mode. The 80286 did not force the A20 line to zero in real mode, however. Therefore, the combination {{mono|F800:8000}} would no longer point to the physical address {{mono|0x00000000}}, but to the address {{mono|0x00100000}}. As a result, programs relying on the address wrap around would no longer work. To remain compatible with such programs, IBM decided to correct the problem on the [[motherboard]].

That was accomplished by inserting a [[logic gate]] on the A20 line between the processor and system bus, which got named ''Gate-A20''. Gate-A20 can be enabled or disabled by software to allow or prevent the address bus from receiving a signal from A20. It is set to non-passing for the execution of older programs that rely on the wrap-around. At boot time, the [[BIOS]] first enables Gate-A20 when it counts and tests all of the system memory, and then disables it before transferring control to the operating system.

Originally, the logic gate was a gate connected to the [[Intel 8042]] keyboard controller.<ref name="Paul_2002_HMA"/> Controlling it was a relatively slow process. Other methods have since been added to allow more efficient [[Computer multitasking|multitasking]] of programs that require this wrap-around with programs that access all of the system memory. There are multiple methods to control the A20 line.<ref name="OSWiki"/>

Disconnecting A20 would not wrap ''all'' memory accesses above 1&nbsp;MB, just those in the 1–2&nbsp;MB, 3–4&nbsp;MB, 5–6&nbsp;MB, etc. ranges. [[Real-mode]] software cared only about the area slightly above 1&nbsp;MB, so the Gate-A20 line was enough.

Enabling the Gate-A20 line is one of the first steps that a [[protected-mode]] [[x86]] [[operating system]] does in the bootup process, often before control has been passed to the [[kernel (operating system)|kernel]] from the [[booting|bootstrap]] (in the case of [[Linux]], for example).

[[Virtual 8086 mode]], introduced with the [[Intel 80386]], allows the A20 wrap-around to be simulated by using the [[virtual memory]] facilities of the processor; physical memory may be mapped to multiple virtual addresses. Thus, the memory mapped at the first megabyte of virtual memory may be mapped again in the second megabyte of virtual memory. The operating system may intercept changes to Gate A20 and make corresponding changes to the virtual-memory address space, which also makes irrelevant the efficiency of Gate-A20 line toggling.