Editing AMD K5 (section)

==Technical details==
[[Image:AMDK5Diagram.png|thumb|250px|K5 core diagram]]
The K5 was based upon an internal highly parallel [[RISC]] processor architecture with an x86 decoding front-end.<ref>{{cite book |url=http://bitsavers.org/components/amd/x86/K86/18524C_K5_Processor_Technical_Reference_Manual_Nov96.pdf |title=AMD-K5 Processor Technical Reference Manual |date=November 1996 |publisher=AMD}}</ref> The K5 offered good x86 compatibility and the in-house-developed test suite proved invaluable on later projects. All models had 4.3 million [[transistor]]s, with five integer units that could process instructions [[Out-of-order execution|out of order]] and one floating-point unit. The [[branch target buffer]] was four times the size of the Pentium's and [[register renaming]] helped overcome register dependencies.<ref>{{cite web |url=http://datasheets.chipdb.org/upload/Unzlbunzl/AMD/18522F%20AMD-K5.pdf |title=AMD-K5 Processor Data Sheet |date=January 1997 |publisher=AMD}}</ref> The chip's [[speculative execution]] of instructions reduced pipeline stalls. It had a 16&nbsp;KB four-way [[CPU cache#Associativity|set-associative]] instruction cache and an 8&nbsp;KB data cache. The floating-point divide and square-root microcode were mechanically proven.<ref>{{cite journal |first1=J. Strother |last1=Moore |first2=Thomas W. |last2=Lynch |first3=Matt |last3=Kaufmann |title=A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program |journal=[[IEEE Transactions on Computers]] |volume=47 |issue=9 |date=September 1998 |pages=913–926 |publisher=[[IEEE Computer Society]] |location=Washington, DC, USA |doi=10.1109/12.713311}}</ref><ref>{{cite journal |first=David M. |last=Russinoff |title=A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode |journal=Formal Methods in System Design |volume=14 |issue=1 |date=January 1999 |pages=75–125 |publisher=[[Kluwer Academic Publishers]] |location=Hingham, MA, USA |doi=10.1023/A:1008669628911 |s2cid=22941018}}</ref>
The floating-point transcendental instructions were implemented in hardware and were faithful to true mathematical results for all operands.<ref>{{cite conference |first1=T. |last1=Lynch |first2=A. |last2=Ahmed |first3=M. |last3=Schulte |first4=T. |last4=Callaway |first5=R. |last5=Tisdale |title=The K5 Transcendental Functions |book-title=Proceedings of the 12th Symposium on Computer Arithmetic |date=19–21 July 1995 |pages=163–170 |publisher=[[IEEE Computer Society]] |location=Washington, DC, USA |isbn=0-8186-7089-4 |doi=10.1109/ARITH.1995.465368}}</ref>