Editing ARM architecture family (section)

==History==

===BBC Micro===
{{Main|BBC Micro}}
[[Acorn Computers]]' first widely successful design was the [[BBC Micro]], introduced in December 1981. This was a relatively conventional machine based on the [[MOS Technology 6502]] CPU but ran at roughly double the performance of competing designs like the [[Apple II]] due to its use of faster [[dynamic random-access memory]] (DRAM). Typical DRAM of the era ran at about 2&nbsp;MHz; Acorn arranged a deal with [[Hitachi]] for a supply of faster 4&nbsp;MHz parts.<ref>{{cite web |last=Fairbairn |first=Douglas |date=31 January 2012 |title=Oral History of Sophie Wilson |url=http://archive.computerhistory.org/resources/access/text/2012/06/102746190-05-01-acc.pdf |access-date=2 February 2016 |url-status=live |archive-url=https://web.archive.org/web/20160303221351/http://archive.computerhistory.org/resources/access/text/2012/06/102746190-05-01-acc.pdf |archive-date=3 March 2016 |df=dmy-all}}</ref>

Machines of the era generally shared memory between the processor and the [[framebuffer]], which allowed the processor to quickly update the contents of the screen without having to perform separate [[input/output]] (I/O). As the timing of the video display is exacting, the video hardware had to have priority access to that memory. Due to a quirk of the 6502's design, the CPU left the memory untouched for half of the time. Thus by running the CPU at 1&nbsp;MHz, the video system could read data during those down times, taking up the total 2&nbsp;MHz bandwidth of the RAM. In the BBC Micro, the use of 4&nbsp;MHz RAM allowed the same technique to be used, but running at twice the speed. This allowed it to outperform any similar machine on the market.<ref name="reghardware">{{cite news |last=Smith |first=Tony |date=30 November 2011 |title=The BBC Micro turns 30 |website=The Register Hardware |url=http://www.reghardware.com/2011/11/30/bbc_micro_model_b_30th_anniversary/ |access-date=12 December 2011 |url-status=live |archive-url=https://web.archive.org/web/20111212044749/http://www.reghardware.com/2011/11/30/bbc_micro_model_b_30th_anniversary/ |archive-date=12 December 2011 |df=dmy-all}}</ref>

===Acorn Business Computer===
{{Main|Acorn Business Computer}}
1981 was also the year that the [[IBM Personal Computer]] was introduced. Using the recently introduced [[Intel 8088]], a [[16-bit computing|16-bit]] CPU compared to the 6502's [[8-bit computing|8-bit]] design, it offered higher overall performance. Its introduction changed the desktop computer market radically: what had been largely a hobby and gaming market emerging over the prior five years began to change to a must-have business tool where the earlier 8-bit designs simply could not compete. Even newer [[32-bit computing|32-bit]] designs were also coming to market, such as the [[Motorola 68000]]<ref>{{cite web |last=Polsson |first=Ken |title=Chronology of Microprocessors |url=https://processortimeline.info/ |url-status=live |archive-url=https://web.archive.org/web/20180809022013/http://processortimeline.info/ |archive-date=2018-08-09 |access-date=2013-09-27 |website=Processortimeline.info}}</ref> and [[National Semiconductor NS32016]].<ref name="leedy198304">{{cite news |last=Leedy |first=Glenn |date=April 1983 |url=https://archive.org/details/byte-magazine-1983-04/page/n53/mode/2up |title=The National Semiconductor NS16000 Microprocessor Family |work=Byte |access-date=22 August 2020 |pages=53–66}}</ref>

Acorn began considering how to compete in this market and produced a new paper design named the [[Acorn Business Computer]]. They set themselves the goal of producing a machine with ten times the performance of the BBC Micro, but at the same price.{{sfn|Evans|2019|loc=6:00}} This would outperform and underprice the PC. At the same time, the recent introduction of the [[Apple Lisa]] brought the [[graphical user interface]] (GUI) concept to a wider audience and suggested the future belonged to machines with a GUI.<ref>{{cite news |url=https://www.electronicsweekly.com/Articles/29/04/1998/7242/ARM39s-way.htm |title=ARM's way |work=[[Electronics Weekly]] |date=29 April 1998 |access-date=26 October 2012 |author=Manners, David |url-status=dead |archive-url=https://web.archive.org/web/20120729024818/http://www.electronicsweekly.com/Articles/29/04/1998/7242/ARM39s-way.htm |archive-date=29 July 2012}}</ref> The Lisa, however, cost $9,995, as it was packed with support chips, large amounts of memory, and a [[hard disk drive]], all very expensive then.{{sfn|Evans|2019|loc=5:30}}

The engineers then began studying all of the CPU designs available. Their conclusion about the existing 16-bit designs was that they were a lot more expensive and were still "a bit crap",{{sfn|Evans|2019|loc=7:45}} offering only slightly higher performance than their BBC Micro design. They also almost always demanded a large number of support chips to operate even at that level, which drove up the cost of the computer as a whole. These systems would simply not hit the design goal.{{sfn|Evans|2019|loc=7:45}} They also considered the new 32-bit designs, but these cost even more and had the same issues with support chips.{{sfn|Evans|2019|loc=8:30}} According to [[Sophie Wilson]], all the processors tested at that time performed about the same, with about a 4&nbsp;Mbit/s bandwidth.<ref>{{cite AV media |url=https://www.youtube.com/watch?v=D4nWLIeBuf4 |archive-url=https://ghostarchive.org/varchive/youtube/20211211/D4nWLIeBuf4 |archive-date=2021-12-11 |url-status=live |title=Sophie Wilson at Alt Party 2009 (Part 3/8)}}{{cbignore}}</ref>{{efn|Using 32-bit words, 4&nbsp;Mbit/s corresponds to 1 [[Instructions per second#Millions of instructions per second (MIPS)|MIPS]].}}

Two key events led Acorn down the path to ARM. One was the publication of a series of reports from the [[University of California, Berkeley]], which suggested that a simple chip design could nevertheless have extremely high performance, much higher than the latest 32-bit designs on the market.<ref name="informit">{{cite book |last=Chisnall |first=David |date=23 August 2010 |url=https://www.informit.com/articles/article.aspx?p=1620207 |title=Understanding ARM Architectures |access-date=26 May 2013}}</ref> The second was a visit by [[Steve Furber]] and Sophie Wilson to the [[Western Design Center]], a company run by [[Bill Mensch]] and his sister, which had become the logical successor to the MOS team and was offering new versions like the [[WDC 65C02]]. The Acorn team saw high school students producing chip layouts on Apple II machines, which suggested that anyone could do it.{{sfn|Evans|2019|loc=9:00}}<ref>{{cite book |last=Furber |first=Stephen B. |year=2000 |title=ARM system-on-chip architecture |publisher=Addison-Wesley |location=Boston |isbn=0-201-67519-6 |title-link=ARM system-on-chip architecture}}</ref> In contrast, a visit to another design firm working on modern 32-bit CPU revealed a team with over a dozen members who were already on revision H of their design and yet it still contained bugs.{{efn|Available references do not mention which design team this was, but given the timing and known history of designs of the era, it is likely this was the National Semiconductor team whose NS32016 suffered from a large number of bugs.}} This cemented their late 1983 decision to begin their own CPU design, the Acorn RISC Machine.{{sfn|Evans|2019|loc=9:50}}

===Design concepts===
The original [[Berkeley RISC]] designs were in some sense teaching systems, not designed specifically for outright performance. To the RISC's basic register-heavy and load/store concepts, ARM added a number of the well-received design notes of the 6502. Primary among them was the ability to quickly serve [[interrupt]]s, which allowed the machines to offer reasonable [[input/output]] performance with no added external hardware. To offer interrupts with similar performance as the 6502, the ARM design limited its physical [[address space]] to 64&nbsp;MB of total addressable space, requiring 26 bits of address. As instructions were 4 bytes (32 bits) long, and required to be aligned on 4-byte boundaries, the lower 2 bits of an instruction address were always zero. This meant the [[program counter]] (PC) only needed to be 24 bits, allowing it to be stored along with the eight bit [[processor flag]]s in a single 32-bit register. That meant that upon receiving an interrupt, the entire machine state could be saved in a single operation, whereas had the PC been a full 32-bit value, it would require separate operations to store the PC and the status flags. This decision halved the interrupt overhead.{{sfn|Evans|2019|loc=23:30}}

Another change, and among the most important in terms of practical real-world performance, was the modification of the [[instruction set]] to take advantage of [[page mode DRAM]]. Recently introduced, page mode allowed subsequent accesses of memory to run twice as fast if they were roughly in the same location, or "page", in the DRAM chip. Berkeley's design did not consider page mode and treated all memory equally. The ARM design added special vector-like memory access instructions, the "S-cycles", that could be used to fill or save multiple registers in a single page using page mode. This doubled memory performance when they could be used, and was especially important for graphics performance.{{sfn|Evans|2019|loc=26:00}}

The Berkeley RISC designs used [[register window]]s to reduce the number of register saves and restores performed in [[procedure call]]s; the ARM design did not adopt this.

Wilson developed the instruction set, writing a simulation of the processor in [[BBC&nbsp;BASIC]] that ran on a BBC Micro with a [[BBC Micro expansion unit#6502 Second Processor|second 6502 processor]].<ref>{{cite web |title=ARM Instruction Set design history with Sophie Wilson (Part 3) |url=https://www.youtube.com/watch?v=QqxThgLTLyk&t=960 |url-status=live |archive-url=https://ghostarchive.org/varchive/youtube/20211211/QqxThgLTLyk |archive-date=2021-12-11 |via=YouTube |date=10 May 2015 |access-date=25 May 2020}}{{cbignore}}</ref><ref>{{cite web |title=Oral History of Sophie Wilson – 2012 Computer History Museum Fellow |url=http://archive.computerhistory.org/resources/access/text/2012/06/102746190-05-01-acc.pdf |work=Computer History Museum |date=31 January 2012 |access-date=25 May 2020}}</ref> This convinced Acorn engineers they were on the right track. Wilson approached Acorn's CEO, [[Hermann Hauser]], and requested more resources. Hauser gave his approval and assembled a small team to design the actual processor based on Wilson's ISA.<ref>{{cite journal |last=Harker |first=T. |date=Summer 2009 |title=ARM gets serious about IP (Second in a two-part series [Associated Editors' View] |url=https://ieeexplore.ieee.org/document/5191430 |journal=IEEE Solid-State Circuits Magazine |volume=1 |issue=3 |pages=8–69 |doi=10.1109/MSSC.2009.933674 |s2cid=36567166 |issn=1943-0590|url-access=subscription }}</ref> The official Acorn RISC Machine project started in October 1983.

===ARM1===
[[File:Acorn-ARM-Evaluation-System.jpg|thumb|right|upright=1.4|ARM1 2nd processor for the BBC&nbsp;Micro]]
Acorn chose [[VLSI Technology]] as the "silicon partner", as they were a source of ROMs and custom chips for Acorn. Acorn provided the design and VLSI provided the layout and production. The first samples of ARM silicon worked properly when first received and tested on 26 April 1985.<ref name="ARM1"/> Known as ARM1, these versions ran at 6&nbsp;MHz.{{sfn|Evans|2019|loc=20:30}}

The first ARM application was as a second processor for the BBC Micro, where it helped in developing simulation software to finish development of the support chips (VIDC, IOC, MEMC), and sped up the [[CAD software]] used in ARM2 development. Wilson subsequently rewrote [[BBC BASIC]] in ARM [[assembly language]]. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, making ARM BBC BASIC an extremely good test for any ARM emulator.

===ARM2===
The result of the simulations on the ARM1 boards led to the late 1986 introduction of the ARM2 design running at 8&nbsp;MHz, and the early 1987 speed-bumped version at 10 to 12&nbsp;MHz.{{efn|Matt Evans notes that it appears the faster versions were simply binned higher, and appear to have no underlying changes.{{sfn|Evans|2019|loc=22:00}}}} A significant change in the underlying architecture was the addition of a [[Booth's multiplication algorithm|Booth multiplier]], whereas formerly multiplication had to be carried out in software.{{sfn|Evans|2019|loc=21:30}} Further, a new Fast Interrupt reQuest mode, FIQ for short, allowed registers 8 through 14 to be replaced as part of the interrupt itself. This meant FIQ requests did not have to save out their registers, further speeding interrupts.{{sfn|Evans|2019|loc=22:0030}}

The first use of the ARM2 were in ARM Evaluations systems, supplied as a second processor for BBC Micro and Master machines, from July 1986,<ref>{{Cite web |title=Chris's Acorns: Acorn OEM Products |url=http://chrisacorns.computinghistory.org.uk/docs/Acorn/OEM/OEM.html |access-date=2025-04-24 |website=chrisacorns.computinghistory.org.uk}}</ref> internal Acorn A500 development machines,<ref>{{Cite web |title=Chris's Acorns: Acorn A500 (prototype) |url=http://chrisacorns.computinghistory.org.uk/Computers/A500.html |access-date=2025-04-24 |website=chrisacorns.computinghistory.org.uk}}</ref> and the [[Acorn Archimedes]] personal computer models A305, A310, and A440, launched on the 6th June 1987.

According to the [[Dhrystone]] benchmark, the ARM2 was roughly seven times the performance of a typical 7&nbsp;MHz 68000-based system like the [[Amiga]] or [[Macintosh SE]]. It was twice as fast as an [[i386|Intel 80386]] running at 16&nbsp;MHz, and about the same speed as a multi-processor [[VAX-11#VAX-11/784|VAX-11/784]] [[superminicomputer]]. The only systems that beat it were the [[Sun SPARC]] and [[R2000 microprocessor|MIPS R2000]] RISC-based [[workstation]]s.{{sfn|Evans|2019|loc=14:00}} Further, as the CPU was designed for high-speed I/O, it dispensed with many of the support chips seen in these machines; notably, it lacked any dedicated [[direct memory access]] (DMA) controller which was often found on workstations. The graphics system was also simplified based on the same set of underlying assumptions about memory and timing. The result was a dramatically simplified design, offering performance on par with expensive workstations but at a price point similar to contemporary desktops.{{sfn|Evans|2019|loc=14:00}}

The ARM2 featured a [[32-bit computing|32-bit]] [[Bus (computing)|data bus]], [[26-bit computing|26-bit]] address space and 27&nbsp;32-bit [[processor register|registers]], of which 16 are accessible at any one time (including the [[program counter|PC]]).<ref>{{cite web |url=https://www.cs.umd.edu/~meesh/cmsc411/website/proj01/arm/armchip.html |title=From one Arm to the next! ARM Processors and Architectures |access-date=31 May 2022}}</ref> The ARM2 had a [[transistor count]] of just 30,000,<ref name="Markus Levy, Convergence Promotions">{{cite web |url=https://reds.heig-vd.ch/share/cours/ReCo/documents/TheHistoryOfTheARMArchitecture.pdf |title=The History of The ARM Architecture: From Inception to IPO |access-date=18 July 2022 |last=Levy |first=Markus}}</ref> compared to Motorola's six-year-older 68000 model with around 68,000. Much of this simplicity came from the lack of [[microcode]], which represents about one-quarter to one-third of the 68000's transistors, and the lack of (like most CPUs of the day) a [[CPU cache|cache]]. This simplicity enabled the ARM2 to have a low power consumption and simpler thermal packaging by having fewer powered transistors. Nevertheless, ARM2 offered better performance than the contemporary 1987 [[IBM PS/2 Model 50]], which initially utilised an [[Intel 80286]], offering 1.8 MIPS @ 10&nbsp;MHz, and later in 1987, the 2 MIPS of the PS/2 70, with its [[i386|Intel 386]] DX @ 16&nbsp;MHz.<ref>{{Cite book |url=http://oldcomputers.net/Amiga_3000_manual.pdf |title=Introducing the Commodore Amiga 3000 |date=1991 |publisher=Commodore-Amiga, Inc.}}</ref><ref>{{Cite web |title=Computer MIPS and MFLOPS Speed Claims 1980 to 1996 |url=http://www.roylongbottom.org.uk/mips.htm#anchorAcorn |access-date=2023-06-17 |website=www.roylongbottom.org.uk}}</ref>

A successor, ARM3, was produced with a 4 KB cache, which further improved performance.<ref name="Chattopadhyay2010">{{cite book |author=Santanu Chattopadhyay |title=Embedded System Design |url=https://books.google.com/books?id=4Bir9Kw059gC&pg=PA9 |year=2010 |publisher=PHI Learning Pvt. Ltd. |isbn=978-81-203-4024-4 |page=9}}</ref> The address bus was extended to 32&nbsp;bits in the ARM6, but program code still had to lie within the first 64 MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags.<ref>{{cite web |url=https://www.heyrick.co.uk/assembler/32bit.html |title=32&nbsp;bit operation |author=Richard Murray}}</ref>

===Advanced RISC Machines Ltd. – ARM6===
[[File:ARMSoCBlockDiagram.svg|right|upright=2.1|thumbnail|Microprocessor-based system on a chip]]

[[File:GPS ARM610 die.JPG|thumb|right|upright=1.4|[[Die (integrated circuit)|Die]] of an ARM610 microprocessor]]
In the late 1980s, [[Apple Inc.|Apple Computer]] and [[VLSI Technology]] started working with Acorn on newer versions of the ARM core. In 1990, Acorn spun off the design team into a new company named Advanced RISC Machines Ltd.,<ref>{{cite web |url=https://www.arm.com/about/company-profile/milestones.php |title=ARM Company Milestones |website=ARM |access-date=8 April 2015 |archive-url=https://web.archive.org/web/20150420050600/https://www.arm.com/about/company-profile/milestones.php |archive-date=20 April 2015 |url-status=dead}}</ref><ref name="andrews-co-verification-of-hardware-and-software-for-ARM-SoC-design">{{cite book |last1=Andrews |first1=Jason |title=Co-verification of hardware and software for ARM SoC design |url=https://archive.org/details/coverificationha00andr_198 |url-access=limited |chapter=3 SoC Verification Topics for the ARM Architecture |publisher=[[Elsevier]] |year=2005 |location=Oxford, UK |pages=[https://archive.org/details/coverificationha00andr_198/page/n93 69] |isbn=0-7506-7730-9 |quote=ARM started as a branch of Acorn Computer in Cambridge, England, with the formation of a joint venture between Acorn, Apple and VLSI Technology. A team of twelve employees produced the design of the first ARM microprocessor between 1983 and 1985.}}</ref><ref name="latimes apple to join acorn">{{cite news |url=https://www.latimes.com/archives/la-xpm-1990-11-28-fi-4993-story.html |title=Apple to Join Acorn, VLSI in Chip-Making Venture |work=Los Angeles Times |date=28 November 1990 |access-date=6 February 2012 |author=Weber, Jonathan |location=Los Angeles |quote=Apple has invested about $3 million (roughly 1.5 million pounds) for a 30% interest in the company, dubbed Advanced Risc Machines Ltd. (ARM) [...]}}</ref> which became ARM Ltd. when its parent company, [[Arm Holdings]] plc, floated on the [[London Stock Exchange]] and [[Nasdaq]] in 1998.<ref>{{cite web |url=https://www.arm.com/miscPDFs/3822.pdf |title=ARM Corporate Backgrounder |website=ARM |archive-url=https://web.archive.org/web/20061004150423/https://www.arm.com/miscPDFs/3822.pdf |archive-date=4 October 2006 |url-status=dead}}</ref> The new Apple–ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used the ARM6-based ARM610 as the basis for their [[Apple Newton]] PDA.

===Early licensees===
In 1994, Acorn used the ARM610 as the main [[central processing unit]] (CPU) in their [[RiscPC]] computers. [[Digital Equipment Corporation|DEC]] licensed the ARMv4 architecture and produced the [[StrongARM]].<ref>{{cite journal |last1=Montanaro |first1=James |first2=Richard T. |last2=Witek |first3=Krishna |last3=Anne |first4=Andrew J. |last4=Black |first5=Elizabeth M. |last5=Cooper |first6=Daniel W. |last6=Dobberpuhl |author-link6=Daniel W. Dobberpuhl |first7=Paul M. |last7=Donahue |first8=Jim |last8=Eno |first9=Gregory W. |last9=Hoeppner |first10=David |last10=Kruckemyer |first11=Thomas H. |last11=Lee |first12=Peter C. M. |last12=Lin |first13=Liam |last13=Madden |first14=Daniel |last14=Murray |first15=Mark H. |last15=Pearce |first16=Sribalan |last16=Santhanam |first17=Kathryn J. |last17=Snyder |first18=Ray |last18=Stephany |first19=Stephen C. |last19=Thierauf |display-authors=1 |date=1997 |url=https://www.hpl.hp.com/hpjournal/dtj/vol9num1/vol9num1art5.pdf |title=A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor |journal=Digital Technical Journal |volume=9 |issue=1 |pages=49–62}}</ref> At 233&nbsp;[[Hertz|MHz]], this CPU drew only one watt (newer versions draw far less). This work was later passed to Intel as part of a lawsuit settlement, and Intel took the opportunity to supplement their [[Intel i960|i960]] line with the StrongARM. Intel later developed its own high performance implementation named [[XScale]], which it has since sold to [[Marvell Technology Group|Marvell]]. Transistor count of the ARM core remained essentially the same throughout these changes; ARM2 had 30,000&nbsp;transistors,<ref name=deMone>{{cite web |last1=DeMone |first1=Paul |title=ARM's Race to Embedded World Domination |url=https://www.realworldtech.com/arms-race/ |website=Real World Technologies |access-date=6 October 2015 |date=9 November 2000}}</ref> while ARM6 grew only to 35,000.<ref>{{cite web |url=https://www.technologyreview.com/article/418585/march-of-the-machines/ |title=March of the Machines |website=technologyreview.com |publisher=[[MIT Technology Review]] |access-date=6 October 2015 |date=20 April 2010 |archive-date=16 October 2015 |archive-url=https://web.archive.org/web/20151016102603/http://www.technologyreview.com/article/418585/march-of-the-machines/ |url-status=dead }}</ref>

===Market share===
In 2005, about 98% of all mobile phones sold used at least one ARM processor.<ref name=Krazit>{{cite news |url=https://www.cnet.com/tech/tech-industry/armed-for-the-living-room/ |title=ARMed for the living room |first=Tom |last=Krazit |date=3 April 2006 |publisher=CNET}}</ref> In 2010, producers of chips based on ARM architectures reported shipments of 6.1&nbsp;billion [[list of products using ARM processors|ARM-based processors]], representing 95% of [[smartphone]]s, 35% of [[integrated digital television|digital television]]s and [[set-top box]]es, and 10% of [[mobile computer]]s. In 2011, the 32-bit ARM architecture was the most widely used architecture in mobile devices and the most popular 32-bit one in embedded systems.<ref name="popular"/> In 2013, 10 billion were produced<ref>{{cite web |url=https://community.arm.com/community/news/blog/2014/02/12/celebrating-50-billion-shipped-arm-powered-chips |title=Celebrating 50 Billion shipped ARM-powered Chips |author1=Tracy Robinson |date=12 February 2014}}</ref> and "ARM-based chips are found in nearly 60 percent of the world's mobile devices".<ref>{{cite web |url=https://www.broadcom.com/blog/chip-design/arms-reach-50-billion-chip-milestone-video/ |title=ARM's Reach: 50 Billion Chip Milestone |author1=Sarah Murry |date=3 March 2014 |archive-url=https://web.archive.org/web/20150916101815/https://www.broadcom.com/blog/chip-design/arms-reach-50-billion-chip-milestone-video/ |archive-date=16 September 2015 |url-status=dead}}</ref>