Editing Back-side bus (section)

==History==

BSB is an improvement over the older practice of using a single [[system bus]], because a single bus typically became a severe [[Von Neumann bottleneck|bottleneck]] as CPUs and memory speeds increased. Due to its dedicated nature, the back-side bus can be optimized for communication with cache, thus eliminating protocol overheads and additional signals that are required on a general-purpose bus.  Furthermore, since a BSB operates over a shorter distance, it can typically operate at higher clock speeds, increasing the computer's overall performance.

Cache connected with a BSB was initially external to the microprocessor [[Die (integrated circuit)|die]], but now is usually on-die.<ref>{{cite web |url= http://www.itworld.com/Comp/1091/CWD010430STO60015/ |archiveurl= https://web.archive.org/web/20010502134148/http://www.itworld.com/Comp/1091/CWD010430STO60015/ |archivedate= 2001-05-02|
title=Buses: frontside and backside|
publisher=[[ITworld]]|
date=2001-04-30}}</ref> In the latter case, the BSB [[Clock signal|clock]] frequency is typically equal to the processor's,<ref>{{cite web|
url=http://www.itworld.com/Comp/1091/CWD010430STO60015/|
archiveurl=https://web.archive.org/web/20010502134148/http://www.itworld.com/Comp/1091/CWD010430STO60015/|
archivedate=2001-05-02|
title=Buses: frontside and backside|
publisher=[[ITworld]]|
date=2001-04-30}}</ref> and the back-side bus can also be made much wider (256-bit, 512-bit) than either off-chip or on-chip FSB.{{Clarify|reason=What is "on-chip FSB" and how does it differ from "off-chip FSB"? Aren't all FSBs made for off-chip communicatio?|date=July 2022}}

[[File:P2 Deschutes open front.jpg|thumb|right|A Pentium II processor module with its cover removed showing the processor on the left and the L2 cache memory on the right]]

The dual-bus architecture was used in a number of designs, including the [[IBM]] and [[Freescale Semiconductor|Freescale]] (formerly the semiconductor division of [[Motorola]]) [[PowerPC]] processors (certain PowerPC [[604e#PowerPC 604|604]] models, the [[PowerPC 7xx]] family,<ref>{{cite web|url=http://news.cnet.com/Monday+a+big+day+for+Apple/2100-1001_3-205119.html|title=Monday a big day for Apple|publisher=CNet|date=1997-11-07}}</ref> and the Freescale [[PowerPC G4|7xxx]] line), as well as the [[Intel Corporation|Intel]] [[Pentium Pro]], [[Pentium II]] and early [[Pentium III]] processors,<ref>{{cite web|
url=http://searchstorage.techtarget.com/sDefinition/0,,sid5_gci213804,00.html|
title=Backside Bus|
publisher=Whatis.com|
date=2001-04-30}}</ref> 
which used it to access their L2 cache (earlier Intel processors accessed the L2 cache over the FSB, while later processors moved it on-chip).