Editing Bus contention (section)

==Description==
Most bus architectures requires devices sharing a bus to follow an arbitration protocol carefully designed to make the likelihood of contention negligible.<ref>{{citation|title = Structured Computer Organization|first = Andrew|last = Tanenbaum|author-link = Andrew Tanenbaum|publisher = [[Prentice Hall]]|pages = 121–124|year = 1990|bibcode = 1990sco..book.....T|edition = 3rd|isbn = 0-13-852872-1}}.</ref> However, when devices on the bus have logic errors, manufacturing defects, or are driven beyond their design speeds, arbitration may break down and contention may result. Contention may also arise on systems which have a programmable [[Memory-mapped I/O|memory mapping]] when illegal values are written to the [[hardware register|registers]] controlling the mapping.
Most small-scale computer systems are carefully designed to avoid bus contention on the [[system bus]]. They use a single device, called [[bus arbiter]], that controls which device is allowed to drive the bus at each instant, so bus contention never happens in normal operation. The standard solution to bus contention between memory devices, such as [[EEPROM]] and [[Static random-access memory|SRAM]], is the [[three-state bus]]<ref name="dunton" /> with a bus arbiter.

Some networks, such as [[Token Ring]], are also designed to avoid bus contention, so bus contention never happens in normal operation.

Most networks are designed with hardware robust enough to tolerate occasional bus contention on the network. [[CAN bus]], [[ALOHAnet]], [[Ethernet]], etc., all experience occasional bus contention in normal operation, but use some protocol (such as [[Multiple Access with Collision Avoidance]], [[carrier-sense multiple access with collision detection]], or [[automatic repeat request]]) to minimize the times that contention occurs, and to re-send data that was corrupted in a [[packet collision]].