Editing CAS latency (section)

==RAM operation background==
{{details|DRAM#Principles of operation}}
Dynamic RAM is arranged in a rectangular array.  Each row is selected by a horizontal ''word line''. Sending a logical high signal along a given row enables the [[MOSFET]]s present in that row, connecting each storage capacitor to its corresponding vertical ''bit line''.  Each bit line is connected to a ''sense amplifier'' that amplifies the small voltage change produced by the storage capacitor. This amplified signal is then output from the DRAM chip as well as driven back up the bit line to ''refresh'' the row.

When no word line is active, the array is idle and the bit lines are held in a precharged<ref>{{cite book
 | last1=Keeth
 | first1=Brent
 | last2=Baker
 | first2=R. Jacob
 | last3=Johnson
 | first3=Brian
 | last4=Lin
 | first4=Feng
 | date=December 4, 2007
 
 | title=DRAM Circuit Design: Fundamental and High-Speed Topics
 | publisher=John Wiley & Sons
 | isbn=978-0470184752
 | url=https://books.google.com/books?id=TgW3LTubREQC
 }}</ref> state, with a voltage halfway between high and low. This indeterminate signal is deflected towards high or low by the storage capacitor when a row is made active.

To access memory, a row must first be selected and loaded into the sense amplifiers.  This row is then ''active,'' and columns may be accessed for read or write.

The CAS latency is the delay between the time at which the column address and the ''column address strobe'' signal are presented to the memory module and the time at which the corresponding data is made available by the memory module.  The desired row must already be active; if it is not, additional time is required.

As an example, a typical 1 [[Gibibyte|GiB]] [[SDRAM]] memory module might contain eight separate one-[[gibibit]] DRAM chips, each offering 128 [[Mebibyte|MiB]] of storage space.  Each chip is divided internally into eight banks of 2<sup>27</sup>=128 [[Mebibit|Mibit]]s, each of which composes a separate DRAM array.  Each bank contains 2<sup>14</sup>=16384 rows of 2<sup>13</sup>=8192 bits each.  One byte of memory (from each chip; 64 bits total from the whole DIMM) is accessed by supplying a 3-bit bank number, a 14-bit row address, and a 13-bit column address.{{citation needed|date=April 2021}}