Editing CDC STAR-100 (section)

==Description==
The STAR had a 64-bit [[Computer architecture|architecture]], consisting of 195 [[Instruction (computer science)|instructions]].<ref name="CAAPP"/> Its main innovation was the inclusion of 65 vector instructions for [[vector processing]]. The operations performed by these instructions were strongly influenced by concepts and [[Operator (computer programming)|operators]] from the [[APL (programming language)|APL]] programming language; in particular, the concept of "control vectors" (vector masks in modern terminology), and several instructions for vector permutation with control vectors, were carried over directly from APL.<ref>{{Cite book |last1=Hockney |first1=R.W. |title=Parallel Computers: Architecture, Programming and Algorithms |last2=Jesshope |first2=C.R. |publisher=Adam Hilger |year=1981 |page=15}}</ref><ref>{{Cite book |last1=Ibbett |first1=R.N |title=Architecture of High Performance Computers, Volume I: Uniprocessors and vector processors |last2=Topham |first2=N.P |publisher=[[Springer-Verlag]] |year=1989 |page=159}}</ref>

The vector instructions operated on vectors that were stored in consecutive locations in main memory; memory addressing was [[Virtual memory|virtual]]. The vector instructions fed an arithmetic [[Instruction pipelining|pipeline]]; a single instruction could add two variable-length vectors of up to 65,535 elements with just one instruction fetch. The STAR also fetched vector operands in 512-bit units (superwords), reducing average memory latency.

Since the memory location of the "next" operand is known, the CPU can fetch the next operands while it is operating on the previous ones. As with instruction pipelines in general, the time needed to complete any one instruction was no better than it was before, but since the CPU is working on a number of data points at once, the overall performance dramatically improves.

Many of the STAR's instructions were complex, especially the ''vector macro'' instructions, which performed complex operations that normally would have required long sequences of instructions. These instructions, along with the STAR's generally complex architecture, was implemented with [[microcode]].<ref name="SA"/>

Main memory had a capacity of 65,536 512-bit [[Word (data type)|words]], called superwords (SWORDs).<ref name="TAoPC"/> Main memory was 32-way [[Interleaved memory|interleaved]] to pipeline memory accesses. It was constructed from [[core memory]] with an [[access time]] of 1.28&nbsp;μs. The main memory was accessed via a 512-bit bus, controlled by the ''storage access controller'' (SAC), which handled requests from the ''stream unit''. The stream unit accesses the main memory through the SAC via three 128-bit data buses, two for reads, and one for writes. There is also a 128-bit data bus for instruction fetch, I/O, and control vector access. The stream unit serves as the control unit, fetching and decoding instructions, initiating memory accesses on the behalf of the pipelined functional units, and controlling instruction execution, among other tasks. It also contains two read buffers and one write buffer for streaming data to the execution units.<ref name="TAoPC"/>

The STAR-100 has two arithmetic pipelines. The first has a floating point adder and multiplier, and the second can execute all scalar instructions. It also contains a floating point adder, multiplier, and divider. Both pipelines are 64-bit for floating point operations and are controlled by microcode. The STAR-100 can split its floating point pipelines into four 32-bit pipelines, doubling the peak performance of the system to 100&nbsp;MFLOPS at the expense of half the precision.<ref name="TAoPC"/>

The STAR-100 uses I/O processors to offload I/O from the CPU. Each I/O processor is a 16-bit [[minicomputer]] with its own main memory of 65,536 words of 16 bits each, which is implemented with core memory. The I/O processors all share a 128-bit data bus to the SAC.