Editing COP8 (section)

==Registers and memory map==
{| class="infobox" style="font-size:88%;width:26em;"
|-
|+ COP8 registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto;" | ''(bit position)''
|-
|colspan="17" | '''Main registers'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" | 
| style="text-align:center;" colspan="8"| A
| style="width:auto; background:white; color:black;"| '''A'''ccumulator
|- style="background:silver;color:black"
| style="text-align:center;" colspan="7"| PCU
| style="text-align:center;" colspan="8"| PCL
| style="background:white; color:black;"| '''P'''rogram&nbsp;'''C'''ounter
|-
|colspan="20" | Note: All other programmer-visible registers and status bits are allocated in RAM.
|}
|}
The COP8 uses separate instruction and data spaces ([[Harvard architecture]]).{{r|basic|p=2-1|comparison|p2=2-4}}  Instruction address space is 15-bit (32&nbsp;KiB maximum), while data addresses are 8-bit (256 bytes maximum, extended via bank-switching).

To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction.  Invalid RAM above the stack reads as all-ones, which is an invalid address.

The CPU has an 8-bit accumulator and 15-bit [[program counter]].  16 additional 8-bit registers (R0–R15) and an 8-bit [[program status word]] are memory mapped.  There are special instructions to access them, but general RAM access instructions may also be used.

The memory map is divided into half RAM and half control registers as follows:
{|class="wikitable"
|+ COP8 data address space
|-
! Addresses || Use
|-
| 0x00–6F || General purpose RAM, used for stack
|-
| 0x70–7F || Unused, reads as all-ones (0xFF) to trap stack underflows
|-
| 0x80–8F || Unused, reads undefined
|-
| 0x90–BF || Additional peripheral control registers
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| 0xC0–CF || Peripheral control registers.
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| 0xD0–DF || General purpose I/O ports L, G, I, C and D
|-
| 0xE0–E8 || Reserved
|-
| 0xE9 || [[Microwire]] shift register
|-
| 0xEA–ED || Timer 1 registers
|-
| 0xEE || CNTRL register, control bits for Microwire & Timer 1
|-
| 0xEF || PSW, CPU program status word
|-
| 0xF0–FB || R0–R11, on-chip RAM mapped as registers
|-
| 0xFC || R12, a.k.a. X, secondary indirect pointer register
|-
| 0xFD || R13, a.k.a. SP, stack pointer register
|-
| 0xFE || R14, a.k.a. B, primary indirect pointer register
|-
| 0xFF || R15, a.k.a. S, data segment extension register
|}
If RAM is not banked, then R15 (S) is just another general-purpose register.  If RAM is banked, then the low half of the data address space (addresses 0x00–7F) is directed to a RAM bank selected by S.  The special purpose registers in the high half of the data address space are always visible.  The data registers at 0xF''x'' can be used to copy data between banks.

RAM banks other than bank 0 have all 128 bytes available.  The stack (addressed via the stack pointer) is always on bank 0, no matter how the S register is set.