Editing CPU cache (section)

=={{Anchor|ICACHE|DCACHE|instruction cache|data cache}}Overview==
When trying to read from or write to a location in the main memory, the processor checks whether the data from that location is already in the cache. If so, the processor will read from or write to the cache instead of the much slower main memory.

Many modern [[desktop computer|desktop]], [[server (computing)|server]], and industrial CPUs have at least three independent levels of caches (L1, L2 and L3) and different types of caches:

; [[Translation lookaside buffer]] (TLB): Used to speed up virtual-to-physical address translation for both executable instructions and data. A single TLB can be provided for access to both instructions and data, or a separate Instruction TLB (ITLB) and data TLB (DTLB) can be provided. However, the TLB cache is part of the [[memory management unit]] (MMU) and not directly related to the CPU caches.

;'''Instruction cache''':
:; [[Micro-operation|MicroOp-cache]]:
:; [[Branch target buffer]]:
:; Instruction cache (I-cache): Used to speed executable instruction fetch

;'''Data cache''':
:; Data cache (D-cache): Used to speed data fetch and store; the data cache is usually organized as a hierarchy of more cache levels (L1, L2, etc.; see also [[#Multi-level caches|multi-level caches]] below).