Editing Cache (computing) (section)

==Motivation==
In memory design, there is an inherent trade-off between capacity and speed because larger capacity implies larger size and thus greater physical distances for signals to travel causing [[propagation delay]]s. There is also a tradeoff between high-performance technologies such as [[Static random-access memory|SRAM]] and cheaper, easily mass-produced commodities such as [[DRAM]], [[flash memory|flash]], or [[hard disk]]s.

The [[Data buffer|buffering]] provided by a cache benefits one or both of [[latency (engineering)|latency]] and [[throughput]] ([[bandwidth (computing)|bandwidth]]).

A larger resource incurs a significant latency for access – e.g. it can take hundreds of clock cycles for a modern 4&nbsp;GHz processor to reach DRAM. This is mitigated by reading large chunks into the cache, in the hope that subsequent reads will be from nearby locations and can be read from the cache. Prediction or explicit [[Cache prefetching|prefetching]] can be used to guess where future reads will come from and make requests ahead of time; if done optimally, the latency is bypassed altogether.

The use of a cache also allows for higher throughput from the underlying resource, by assembling multiple fine-grain transfers into larger, more efficient requests. In the case of DRAM circuits, the additional throughput may be gained by using a wider data bus.